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公开(公告)号：US11620077B2
公开(公告)日：2023-04-04
申请号：US17224747
申请日：2021-04-07
摘要： An embodiment method of accessing a memory for reading and/or writing data comprises generating a memory transaction request comprising a burst of memory access requests towards a set of memory locations in the memory, the memory locations having respective memory addresses. The method further comprises transmitting via an interconnect bus to a memory controller circuit coupled to the memory a first signal conveying the memory transaction request and a second signal conveying information for mapping the burst of memory access requests onto respective memory addresses of the memory locations in the memory. The method further comprises computing, as a function of the information conveyed by the second signal, respective memory addresses of the memory locations, and accessing the memory locations to read data from the memory locations and/or to write data into the memory locations.
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公开(公告)号：US20220350764A1
公开(公告)日：2022-11-03
申请号：US17811209
申请日：2022-07-07
IPC分类号： G06F13/28 , G06F9/46 , G06F13/37 , G06F13/372 , G06F17/14
摘要： An embodiment circuit comprises a plurality of processing units, a plurality of data memory banks configured to store data, and a plurality of coefficient memory banks configured to store twiddle factors for fast Fourier transform processing. The processing units are configured to fetch, at each of the FFT computation stages, input data from the data memory banks with a burst read memory transaction, fetch, at each of the FFT computation cycles, different twiddle factors in a respective set of the twiddle factors from different coefficient memory banks of the coefficient memory banks, process the input data and the set of twiddle factors to generate output data, and store, at each of the FFT computation stages, the output data into the data memory banks with a burst write memory transaction.
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公开(公告)号：US20220012199A1
公开(公告)日：2022-01-13
申请号：US17339083
申请日：2021-06-04
IPC分类号： G06F13/28 , G06F13/372 , G06F13/37 , G06F17/14 , G06F9/46
摘要： An embodiment circuit comprises a plurality of processing units, a plurality of data memory banks configured to store data, and a plurality of coefficient memory banks configured to store twiddle factors for fast Fourier transform processing. The processing units are configured to fetch, at each of the FFT computation stages, input data from the data memory banks with a burst read memory transaction, fetch, at each of the FFT computation cycles, different twiddle factors in a respective set of the twiddle factors from different coefficient memory banks of the coefficient memory banks, process the input data and the set of twiddle factors to generate output data, and store, at each of the FFT computation stages, the output data into the data memory banks with a burst write memory transaction.
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公开(公告)号：US20210342091A1
公开(公告)日：2021-11-04
申请号：US17224747
申请日：2021-04-07
摘要： An embodiment method of accessing a memory for reading and/or writing data comprises generating a memory transaction request comprising a burst of memory access requests towards a set of memory locations in the memory, the memory locations having respective memory addresses. The method further comprises transmitting via an interconnect bus to a memory controller circuit coupled to the memory a first signal conveying the memory transaction request and a second signal conveying information for mapping the burst of memory access requests onto respective memory addresses of the memory locations in the memory. The method further comprises computing, as a function of the information conveyed by the second signal, respective memory addresses of the memory locations, and accessing the memory locations to read data from the memory locations and/or to write data into the memory locations.
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公开(公告)号：US11675720B2
公开(公告)日：2023-06-13
申请号：US17811209
申请日：2022-07-07
IPC分类号： G06F13/28 , G06F9/46 , G06F13/37 , G06F13/372 , G06F17/14
CPC分类号： G06F13/287 , G06F9/467 , G06F13/37 , G06F13/372 , G06F17/142
摘要： An embodiment circuit comprises a plurality of processing units, a plurality of data memory banks configured to store data, and a plurality of coefficient memory banks configured to store twiddle factors for fast Fourier transform processing. The processing units are configured to fetch, at each of the FFT computation stages, input data from the data memory banks with a burst read memory transaction, fetch, at each of the FFT computation cycles, different twiddle factors in a respective set of the twiddle factors from different coefficient memory banks of the coefficient memory banks, process the input data and the set of twiddle factors to generate output data, and store, at each of the FFT computation stages, the output data into the data memory banks with a burst write memory transaction.
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公开(公告)号：US11461257B2
公开(公告)日：2022-10-04
申请号：US17339083
申请日：2021-06-04
IPC分类号： G06F13/28 , G06F9/46 , G06F13/37 , G06F13/372 , G06F17/14
摘要： An embodiment circuit comprises a plurality of processing units, a plurality of data memory banks configured to store data, and a plurality of coefficient memory banks configured to store twiddle factors for fast Fourier transform processing. The processing units are configured to fetch, at each of the FFT computation stages, input data from the data memory banks with a burst read memory transaction, fetch, at each of the FFT computation cycles, different twiddle factors in a respective set of the twiddle factors from different coefficient memory banks of the coefficient memory banks, process the input data and the set of twiddle factors to generate output data, and store, at each of the FFT computation stages, the output data into the data memory banks with a burst write memory transaction.
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公开(公告)号：US20220180959A1
公开(公告)日：2022-06-09
申请号：US17453811
申请日：2021-11-05
摘要： A device includes a set of processing circuits arranged in subsets, a set of data memory banks coupled to a memory controller, a control unit, and an interconnect network. The processing circuits are configurable to read first input data from the data memory banks via the interconnect network and the memory controller, process the first input data to produce output data, and write the output data into the data memory banks via the interconnect network and the memory controller. The hardware accelerator device includes a set of configurable lock-step control units which interface the processing circuits to the interconnect network. Each configurable lock-step control unit is coupled to a subset of processing circuits and is selectively activatable to operate in a first operation mode, or in a second operation mode.
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8.发明申请公开(公告)号：US20190107620A1
公开(公告)日：2019-04-11
申请号：US16215037
申请日：2018-12-10
IPC分类号： G01S13/93 , G01S7/292 , G01S13/524 , G01S7/28
摘要： An accelerator device for use in generating a list of potential targets in a radar system, such as an anti-collision radar for a motor vehicle, may process radar data signals arranged in cells stored in a system memory. A cell under test in is identified as a potential target if the cell under test is a local peak over boundary cells and is higher than a certain threshold calculated by sorting range and velocity radar data signals arranged in windows. The cells identified as a potential target are sorted in a sorted list of potential targets. The accelerator device may include a double-buffering local memory for storing cell under test and boundary cell data; and a first and a second sorting unit for performing concurrent sorting of the radar data signals arranged in windows and the cells identified as a potential target in pipeline with accesses to the system memory.
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公开(公告)号：US11742049B2
公开(公告)日：2023-08-29
申请号：US17453811
申请日：2021-11-05
CPC分类号： G11C29/42 , G11C29/12015 , G11C29/18 , G11C29/4401
摘要： A device includes a set of processing circuits arranged in subsets, a set of data memory banks coupled to a memory controller, a control unit, and an interconnect network. The processing circuits are configurable to read first input data from the data memory banks via the interconnect network and the memory controller, process the first input data to produce output data, and write the output data into the data memory banks via the interconnect network and the memory controller. The hardware accelerator device includes a set of configurable lock-step control units which interface the processing circuits to the interconnect network. Each configurable lock-step control unit is coupled to a subset of processing circuits and is selectively activatable to operate in a first operation mode, or in a second operation mode.
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公开(公告)号：US20150268133A1
公开(公告)日：2015-09-24
申请号：US14218482
申请日：2014-03-18
发明人： Om Ranjan , Giampiero Borgonovo , Deepak Baranwal
IPC分类号： G01M99/00
CPC分类号： G06F11/0736 , G05B19/0428 , G05B23/0254 , G05B2219/2637 , G06F11/2205 , G06F11/3013
摘要： A safety system monitors faults in an embedded control system. The embedded control system is modeled to produce one or more model check values by calculating how many clock cycles will pass between an initialization time point and at least one event time point for a specific event. The initialization time point is a certain point in an initialization function of a scheduler in the embedded control system. The at least one event time point is an expected number of clock cycles to pass before a specific event occurs. In operation, the embedded control system is initialized, a current clock cycle counter value is retrieved at a certain point in the initialization, and either an occurrence or an absence of an occurrence of a scheduled event is recognized. A current clock cycle value is recorded upon the recognition, and a mathematic check value is produced from the clock cycle value stored at the certain point in the initialization and the clock cycle value recorded upon the recognition. Subsequently, the model check value is compared to the mathematic check value, and action is taken based on the comparison.
摘要翻译： 安全系统监控嵌入式控制系统中的故障。 嵌入式控制系统被建模为通过计算在特定事件的初始化时间点和至少一个事件时间点之间经过多少个时钟周期来产生一个或多个模型检查值。 初始化时间点是嵌入式控制系统中的调度器的初始化功能中的某一点。 至少一个事件时间点是在特定事件发生之前要通过的期望数量的时钟周期。 在操作中，初始化嵌入式控制系统，在初始化中的某一点检索当前的时钟周期计数器值，并且识别调度事件的发生或不存在。 在识别时记录当前时钟周期值，并且从存储在初始化中的某一点的时钟周期值和在识别时记录的时钟周期值产生数学校验值。 随后，将模型检查值与数学检查值进行比较，并根据比较进行动作。
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