公开(公告)号：US20230117101A1

公开(公告)日：2023-04-20

申请号：US17959797

申请日：2022-10-04

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Marco CIGNOLI ,  Vanni POLETTO

IPC: H02M3/155 ,  G01R19/10 ,  B60L3/12 ,  H02M1/08

Abstract: Provided is a circuit including a switching transistor having a control terminal configured to receive a control signal and having a current flow path therethrough. The switching transistor becomes conductive in response to the control signal having a first value. The current flow path through the switching transistor provides a current flow line between two nodes. In a non-conductive state, a voltage drop stress is across the switching transistor. The circuit comprises a sense transistor that is coupled to and a scaled replica of the switching transistor. The sense transistor has a sense current therethrough. The sense current is indicative of the current of the switching transistor. The circuit includes coupling circuitry configured to apply the voltage drop stress across the sense transistor in response to the switching transistor being non-conductive. In the non-conductive state, the voltage drop stress is replicated across both the switching transistor and the sense transistor.

公开(公告)号：US20220329252A1

公开(公告)日：2022-10-13

申请号：US17713033

申请日：2022-04-04

Applicant: STMicroelectronics S.r.l.

Inventor： Daniele OREGGIA ,  Marco CIGNOLI

IPC: H03M1/10 ,  H03M1/68 ,  H03M1/66 ,  H03M1/56

Abstract: An electronic circuit includes first and second channels which respectively receive first and second analog signals. The first channel includes a first digital to analog converter having an output coupled to a first input of a first sign comparator, and the second channel includes a second digital to analog converter. A switch network selectively couples, upon reception of a self-test mode signal signaling a test phase, an output of the second digital to analog converter to a second input of the first sign comparator. A ramp generation circuit supplies to the first digital to analog converter and the second digital to analog converter two identical ramps of digital codes, which are shifted by a programmable offset with respect to one another. A checking circuit issues a test status signal based on the output of the first sign comparator.