公开(公告)号：US20220329252A1

公开(公告)日：2022-10-13

申请号：US17713033

申请日：2022-04-04

Applicant: STMicroelectronics S.r.l.

Inventor： Daniele OREGGIA ,  Marco CIGNOLI

IPC: H03M1/10 ,  H03M1/68 ,  H03M1/66 ,  H03M1/56

Abstract: An electronic circuit includes first and second channels which respectively receive first and second analog signals. The first channel includes a first digital to analog converter having an output coupled to a first input of a first sign comparator, and the second channel includes a second digital to analog converter. A switch network selectively couples, upon reception of a self-test mode signal signaling a test phase, an output of the second digital to analog converter to a second input of the first sign comparator. A ramp generation circuit supplies to the first digital to analog converter and the second digital to analog converter two identical ramps of digital codes, which are shifted by a programmable offset with respect to one another. A checking circuit issues a test status signal based on the output of the first sign comparator.