公开(公告)号：US11935992B2

公开(公告)日：2024-03-19

申请号：US17965443

申请日：2022-10-13

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Romain Coffy ,  Remi Brechignac ,  Jean-Michel Riviere

IPC: H01L33/52 ,  H01L31/0203 ,  H01L31/0216 ,  H01L33/44 ,  H01L33/62

CPC classification number: H01L33/52 ,  H01L31/0203 ,  H01L31/02164 ,  H01L33/44 ,  H01L33/62

Abstract: An electronic device includes a first electronic component and a second electronic. Each electronic component includes a carrier substrate having a back side and a front side, an electronic chip including an integrated optical element, an overmolded transparent block encapsulating the electronic chip above the carrier substrate, and electrical connections between the electronic chip and electrical contacts of the carrier substrate. An overmolded grid encapsulates and holds the first and second electronic components. The grid is configured so that sides of the first and second electronic components are at least partially exposed.

公开(公告)号：US11387381B2

公开(公告)日：2022-07-12

申请号：US17071694

申请日：2020-10-15

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Romain Coffy ,  Remi Brechignac ,  Jean-Michel Riviere

IPC: H01L31/16 ,  H01L23/00

Abstract: An optoelectronic device includes an emitter of light rays and a receiver of light rays. The emitter is encapsulated in a transparent block. An opaque conductive layer is applied to a top surface and a side surface of the transparent block. The receiver is mounted to the opaque conductive layer at the top surface. An electrical connection is made between the receiver and the opaque conductive layer. A conductive strip is also mounted to the side surface of the transparent block and isolated from the opaque conductive layer. A further electrical connection is made between the receiver and the conductive strip.

公开(公告)号：US11380663B2

公开(公告)日：2022-07-05

申请号：US17006092

申请日：2020-08-28

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Romain Coffy ,  Remi Brechignac ,  Jean-Michel Riviere

IPC: H01L25/16 ,  H01L31/02 ,  H01L31/0203 ,  H01L33/52 ,  H01L33/62

Abstract: An opaque dielectric carrier and confinement substrate is formed by a stack of layers laminated on each other. The stack includes a solid back layer and a front frame having a peripheral wall and an intermediate partition which delimits two cavities located on top of the solid back layer and on either side of the intermediate partition. Electronic integrated circuit (IC) chips are located inside the cavities and mounted on top of the solid back layer. Each IC chip includes an integrated optical element. Electrical connections are provided between the IC chips and back electrical contacts of the solid back layer. Transparent encapsulation blocks are molded in the cavities to embed the IC chips.

公开(公告)号：US10998470B2

公开(公告)日：2021-05-04

申请号：US16218906

申请日：2018-12-13

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS

Inventor： Jean-Michel Riviere ,  Romain Coffy ,  Karine Saxod

IPC: H01L33/48 ,  H01L33/00 ,  H01L33/58 ,  H05K5/03 ,  H01L31/12 ,  H01L31/0232 ,  H01L31/0203 ,  H01L31/18 ,  H01L31/16

Abstract: A cover for an electronic circuit package, including an element having peripheral portions housed in an inner groove of a through opening.

公开(公告)号：US10903388B2

公开(公告)日：2021-01-26

申请号：US16377379

申请日：2019-04-08

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Jean-Michel Riviere

IPC: H01L31/167 ,  H01L31/02 ,  H01L23/00 ,  H01L31/0232 ,  G01V8/20 ,  H01L31/0203 ,  H01L25/16 ,  H01L31/173 ,  H01L25/065

Abstract: A main carrier wafer includes a first integrated network of electronic connections between front and back faces. A first electronic chip is mounted to the front face of the main carrier wafer and connected to the network of electronic connections of the main carrier wafer. A secondary carrier wafer includes a platform that extends over the first chip and a base the protrudes backwards with respect to the platform to a back end face facing the main wafer. A second integrated network of electronic connections is provided within the secondary carrier wafer. A second electronic chip is mounted on top of the platform and connected to the second integrated network. The second integrated network is further connected to the main carrier wafer at the back end face.

公开(公告)号：US12288961B2

公开(公告)日：2025-04-29

申请号：US17223649

申请日：2021-04-06

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Fabien Quercia ,  Jean-Michel Riviere

IPC: H01S5/02234 ,  G01S7/481 ,  H01L31/0203 ,  H01L31/0232 ,  H01S5/00 ,  H01S5/0236 ,  H01S5/40

Abstract: An electronic device includes a base substrate having a mounting face. An electronic chip is fastened onto the mounting face of the base substrate. A transparent encapsulation structure is bonded onto the base substrate. The transparent encapsulation structure includes a housing with an internal cavity defining a chamber housing the electronic chip. The encapsulation structure has an external face that supports a light-filtering optical wafer located facing an optical element of the electronic chip. An opaque cover covers the transparent encapsulation structure and includes a local opening facing the light-filtering optical wafer.

公开(公告)号：US11916353B2

公开(公告)日：2024-02-27

申请号：US17229710

申请日：2021-04-13

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS

Inventor： Fabien Quercia ,  Jean-Michel Riviere

IPC: H01S5/02345 ,  H01L23/00

CPC classification number: H01S5/02345 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/12042 ,  H01L2924/18165

Abstract: Electronic device comprising a support substrate having a mounting face and an electronic chip having a rear face bonded on the mounting face by a volume of adhesive, wherein the support substrate comprises a plurality of wedging elements projecting from the mounting face so as to hold the chip bearing on contact areas of the wedging elements in a position substantially parallel to the mounting face of the support substrate.

公开(公告)号：US11527511B2

公开(公告)日：2022-12-13

申请号：US16692720

申请日：2019-11-22

Applicant: STMicroelectronics Pte Ltd ,  STMicroelectronics (Grenoble 2) SAS

Inventor： David Gani ,  Jean-Michel Riviere

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/498 ,  H01L23/528

Abstract: An electronic device includes a support substrate to which a first electronic chip and a second electronic chip are mounted in a position situated on top of one another. First electrical connection elements are interposed between the first electronic chip and the support substrate. Second electrical connection elements are interposed between the second electronic chip and the support substrate and are situated at a distance from a periphery of the first electronic chip. Third electrical connection elements are interposed between the first electronic chip and the second electronic chip.

公开(公告)号：US10941921B2

公开(公告)日：2021-03-09

申请号：US16552419

申请日：2019-08-27

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS

Inventor： Romain Coffy ,  Jean-Michel Riviere

IPC: F21V17/10 ,  F21V23/00 ,  F21V17/08 ,  F21V3/04 ,  F21V17/06 ,  F21Y115/30

Abstract: The present disclosure relates to a light-emitting device comprising: a light source mounted on a substrate; a wire for providing a supply voltage or activation signal to the light source, a cap covering the light source and having a diffuser adapted to diffuse light generated by the light source; and either: a volume of glue fixing an intermediate section of the wire to the cap; or an arm fixed to the cap and extending between the intermediate section of the wire and the substrate.

公开(公告)号：US20170345805A1

公开(公告)日：2017-11-30

申请号：US15166726

申请日：2016-05-27

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Norbert Chevrier ,  Benoit Besancon ,  Jean-Michel Riviere

IPC: H01L25/16 ,  H01L25/00 ,  H01L23/522 ,  H01L21/768 ,  H01L23/31 ,  H01L23/29 ,  H01L27/02 ,  H01L23/00

CPC classification number: H01L25/16 ,  H01L21/76804 ,  H01L21/76879 ,  H01L23/3135 ,  H01L23/5226 ,  H01L23/60 ,  H01L24/16 ,  H01L25/50 ,  H01L27/0251 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/15331

Abstract: Disclosed herein is an electronic device including a substrate having a conductive area formed thereon. A first molding level is stacked on the substrate. A die is formed on the substrate and within the first molding level. A second molding level is stacked on the first molding level. At least one passive component is within the second molding level. A conductive structure extends between the second molding level and the substrate and electrically couples the at least one passive component to the conductive area.