公开(公告)号：US20160351486A1

公开(公告)日：2016-12-01

申请号：US14722872

申请日：2015-05-27

Applicant: STATS ChipPAC, Ltd.

Inventor： JinHee Jung ,  HyungSang Park ,  SungSoo Kim

IPC: H01L23/498 ,  H01L49/02 ,  H01L21/48

CPC classification number: H01L28/40 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/25 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2224/2518 ,  H01L2224/32225 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/83005 ,  H01L2224/92144 ,  H05K1/185 ,  H05K3/4664 ,  H05K2201/10015

Abstract: A semiconductor device comprises a first conductive layer. A second conductive layer is formed over the first conductive layer. A semiconductor component is disposed over the first conductive layer. The second conductive layer lies in a plane between a top surface of the semiconductor component and a bottom surface of the semiconductor component. A third conductive layer is formed over the semiconductor component opposite the first conductive layer. The semiconductor device includes a symmetrical structure. A first insulating layer is formed between the first conductive layer and semiconductor component. A second insulating layer is formed between the semiconductor component and third conductive layer. A height of the first insulating layer between the first conductive layer and semiconductor component is between 90% and 110% of a height of the second insulating layer between the semiconductor component and third conductive layer. The semiconductor component includes a passive device.

Abstract translation: 半导体器件包括第一导电层。 在第一导电层上形成第二导电层。 半导体部件设置在第一导电层上。 第二导电层位于半导体部件的顶表面和半导体部件的底表面之间的平面中。 在与第一导电层相对的半导体部件上形成第三导电层。 半导体器件包括对称结构。 在第一导电层和半导体部件之间形成第一绝缘层。 在半导体部件和第三导电层之间形成第二绝缘层。 第一导电层和半导体部件之间的第一绝缘层的高度在半导体部件和第三导电层之间的第二绝缘层的高度的90％至110％之间。 半导体部件包括无源器件。

公开(公告)号：US20130134586A1

公开(公告)日：2013-05-30

申请号：US13727116

申请日：2012-12-26

Applicant: STATS ChipPAC, Ltd.

Inventor： KiYoun Jang ,  SungSoo Kim ,  YongHee Kang

IPC: H01L23/498

CPC classification number: H01L23/49811 ,  H01L21/4846 ,  H01L21/6835 ,  H01L23/498 ,  H01L23/49827 ,  H01L24/06 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2224/0401 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H05K3/108 ,  H05K3/205 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/097 ,  H05K2201/09736 ,  H05K2203/049 ,  H05K2203/1476 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate, a first recessed conductive layer embedded and recessed into a first surface of the substrate, and a first raised conductive layer disposed above the first surface. A first vertical offset exists between an upper surface of the first recessed conductive layer and an upper surface of the first raised conductive layer. The device includes a second recessed conductive layer embedded and recessed into a second surface of the substrate. The second surface of the substrate is opposite the first surface. The device includes a second raised conductive layer disposed beneath the second surface and an interconnect structure disposed on the first recessed and raised conductive layers and the second recessed and raised conductive layers. A second vertical offset exists between a lower surface of the second recessed conductive layer and a lower surface of the second recessed conductive layer.

Abstract translation: 半导体器件包括衬底，嵌入并凹入到衬底的第一表面中的第一凹陷导电层和设置在第一表面上方的第一凸起导电层。 在第一凹陷导电层的上表面和第一凸起导电层的上表面之间存在第一垂直偏移。 该器件包括嵌入并凹入到衬底的第二表面中的第二凹陷导电层。 基板的第二表面与第一表面相对。 该装置包括设置在第二表面下方的第二凸起导电层和设置在第一凹入和凸起导电层上的互连结构和第二凹入和凸起导电层。 在第二凹陷导电层的下表面和第二凹陷导电层的下表面之间存在第二垂直偏移。

公开(公告)号：US09837484B2

公开(公告)日：2017-12-05

申请号：US14722872

申请日：2015-05-27

Applicant: STATS ChipPAC, Ltd.

Inventor： JinHee Jung ,  HyungSang Park ,  SungSoo Kim

IPC: H01L23/498 ,  H01L49/02 ,  H01L23/538 ,  H01L21/683 ,  H01L23/00 ,  H01L23/50 ,  H01L21/48

CPC classification number: H01L28/40 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/25 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2224/2518 ,  H01L2224/32225 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/83005 ,  H01L2224/92144 ,  H05K1/185 ,  H05K3/4664 ,  H05K2201/10015

Abstract: A semiconductor device comprises a first conductive layer. A second conductive layer is formed over the first conductive layer. A semiconductor component is disposed over the first conductive layer. The second conductive layer lies in a plane between a top surface of the semiconductor component and a bottom surface of the semiconductor component. A third conductive layer is formed over the semiconductor component opposite the first conductive layer. The semiconductor device includes a symmetrical structure. A first insulating layer is formed between the first conductive layer and semiconductor component. A second insulating layer is formed between the semiconductor component and third conductive layer. A height of the first insulating layer between the first conductive layer and semiconductor component is between 90% and 110% of a height of the second insulating layer between the semiconductor component and third conductive layer. The semiconductor component includes a passive device.

公开(公告)号：US08742566B2

公开(公告)日：2014-06-03

申请号：US13727116

申请日：2012-12-26

Applicant: STATS ChipPAC, Ltd.

Inventor： KiYoun Jang ,  SungSoo Kim ,  YongHee Kang

IPC: H01L23/04

CPC classification number: H01L23/49811 ,  H01L21/4846 ,  H01L21/6835 ,  H01L23/498 ,  H01L23/49827 ,  H01L24/06 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2224/0401 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H05K3/108 ,  H05K3/205 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/097 ,  H05K2201/09736 ,  H05K2203/049 ,  H05K2203/1476 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate, a first recessed conductive layer embedded and recessed into a first surface of the substrate, and a first raised conductive layer disposed above the first surface. A first vertical offset exists between an upper surface of the first recessed conductive layer and an upper surface of the first raised conductive layer. The device includes a second recessed conductive layer embedded and recessed into a second surface of the substrate. The second surface of the substrate is opposite the first surface. The device includes a second raised conductive layer disposed beneath the second surface and an interconnect structure disposed on the first recessed and raised conductive layers and the second recessed and raised conductive layers. A second vertical offset exists between a lower surface of the second recessed conductive layer and a lower surface of the second recessed conductive layer.

Abstract translation: 半导体器件包括衬底，嵌入并凹入到衬底的第一表面中的第一凹陷导电层和设置在第一表面上方的第一凸起导电层。 在第一凹陷导电层的上表面和第一凸起导电层的上表面之间存在第一垂直偏移。 该器件包括嵌入并凹入到衬底的第二表面中的第二凹陷导电层。 基板的第二表面与第一表面相对。 该装置包括设置在第二表面下方的第二凸起导电层和设置在第一凹入和凸起导电层上的互连结构和第二凹入和凸起导电层。 在第二凹陷导电层的下表面和第二凹陷导电层的下表面之间存在第二垂直偏移。