公开(公告)号：US20200371715A1

公开(公告)日：2020-11-26

申请号：US16707744

申请日：2019-12-09

申请人： SK hynix Inc.

发明人： Joo Young LEE

IPC分类号： G06F3/06

摘要： Provided herein may be a storage device and a method of operating the storage device. A memory controller may include a storage area manager and a write operation controller. The storage area manager may allocate a plurality of memory devices to a first group and a second group in response to a storage area setting command. The write operation controller may control a group selected from the first group and the second group according to a type of a write request to store write data. At least one memory devices in the first group includes memory blocks storing n data bits. At least one memory devices in the second group includes memory blocks storing m data bits.

公开(公告)号：US20200097408A1

公开(公告)日：2020-03-26

申请号：US16523301

申请日：2019-07-26

申请人： SK hynix Inc.

发明人： Joo Young LEE ,  Hoe Seung JUNG

IPC分类号： G06F12/0815

摘要： A data storage device includes a memory cell array comprising a plurality of pages each including K memory cells of which each stores N bits therein, where N and K are positive numbers greater than or equal to 2, wherein each of the pages stores one page data constituted by N subpage data each having K bits; a cache buffer receiving and caching N subpage data of first page data from a controller; and a page buffer sequentially buffering the respective cached N subpage data of the first page data and store the respective buffered N subpage data of the first page data in the memory cell array, wherein when a write operation for Mth subpage data of the first page data is completed, the cache buffer receives and caches Mth subpage data of second page data from the controller, where M is a positive number less than N.

公开(公告)号：US20190332505A1

公开(公告)日：2019-10-31

申请号：US16212331

申请日：2018-12-06

申请人： SK hynix Inc.

发明人： Hoe Seung JUNG ,  Joo Young LEE

IPC分类号： G06F11/20 ,  G11C16/10

摘要： In a memory controller included in a memory system for processing a program operation fail, the memory controller controls a plurality of memory devices commonly coupled to a channel, the plurality of memory devices respectively performing preset program operations, and includes: a buffer memory for storing data to be stored in the plurality of memory devices, based on a buffer memory index; and a program error processor for acquiring fail data corresponding to a program operation fail from a fail memory device and acquiring reprogram data that is data to be stored together with the fail data, based on the buffer memory index.

公开(公告)号：US20190267073A1

公开(公告)日：2019-08-29

申请号：US16139573

申请日：2018-09-24

申请人： SK hynix Inc.

发明人： Joo Young LEE

IPC分类号： G11C11/408 ,  G06F12/0871 ,  G06F12/0882 ,  G11C7/10 ,  G11C11/4099 ,  G11C11/4097

摘要： The semiconductor memory device includes a memory cell array, a page buffer, a cache buffer, and a control logic. The memory cell array includes a plurality of memory blocks. The page buffer senses data of a selected page of the memory cell array. The cache buffer temporarily stores the data sensed by the page buffer. The control logic controls operations of the page buffer and the cache buffer to read data stored in the memory cell array. The control logic controls operations of the page buffer and the cache buffer, based on a cache-normal state of the semiconductor memory device.

公开(公告)号：US20190266083A1

公开(公告)日：2019-08-29

申请号：US16276424

申请日：2019-02-14

申请人： SK hynix Inc.

发明人： Joo Young LEE ,  Sung Kwan HONG

IPC分类号： G06F12/02 ,  G06F12/1009 ,  G06F11/30

摘要： A controller for controlling a nonvolatile memory device comprising: a read count table including a plurality of read count data, wherein each of the read count data includes a read count value for one data storage region; a read count address table including a read count address indicating an address of a memory region where the read count data is stored; a flash translation layer (FTL) configured to control an operation of the nonvolatile memory device, and manage the read count table and the read count address table; and a flash interface layer (FIL) configured to control data communication between the FTL and the nonvolatile memory device, and update the read count value based on the read count address when read operation is performed on the data storage region.

公开(公告)号：US20190012081A1

公开(公告)日：2019-01-10

申请号：US15832966

申请日：2017-12-06

申请人： SK hynix Inc.

发明人： Joo Young LEE ,  Kyeong Rho Kim ,  Kyung Hoon Lee

IPC分类号： G06F3/06 ,  G06F12/02 ,  G06F12/0891 ,  G06F12/0868 ,  G06F12/1009

摘要： Provided herein may be a storage device and a method of operating the same. A memory controller for controlling a memory device including a plurality of memory blocks having improved read performance may include a random read workload control, unit configured to control a state of a random read workload such that the random read workload is in any one of a set state and a clear state depending on a random read count obtained by counting a number of random read requests that are inputted from an external host; and a random read processing unit configured to retrieve a physical address corresponding to a logical address of the respective random read requests depending on the state of the random read workload.

公开(公告)号：US20240184486A1

公开(公告)日：2024-06-06

申请号：US18306163

申请日：2023-04-24

申请人： SK hynix Inc.

发明人： Hoe Seung JUNG ,  Do Hyung KIM ,  Joo Young LEE ,  Sung Kwan HONG

IPC分类号： G06F3/06

CPC分类号： G06F3/0659 ,  G06F3/061 ,  G06F3/064 ,  G06F3/0679

摘要： A storage device may determine write throughput based on a plurality of write commands received from the outside of the storage device, and write target data write-requested from the outside to a first memory area including one or more of a plurality of first type memory blocks or a second memory area including one or more of a second type memory blocks according to whether the write throughput is greater than or equal to a threshold throughput. The first type memory blocks may operate at a higher speed than the second type memory blocks.

公开(公告)号：US20240176747A1

公开(公告)日：2024-05-30

申请号：US18184241

申请日：2023-03-15

申请人： SK hynix Inc.

发明人： Hoe Seung JUNG ,  Do Hyung KIM ,  Chi Heon KIM ,  Joo Young LEE

IPC分类号： G06F12/10

CPC分类号： G06F12/10 ,  G11C16/06

摘要： A storage device may load, between a first time point at which information on candidate memory regions among a plurality of memory regions is started to be sent to an external device and a second time point at which a command requesting a map segment for a target memory region among the plurality of memory regions is received from the external device, all or a part of map segments corresponding to the candidate memory regions into a buffer.

公开(公告)号：US20210349646A1

公开(公告)日：2021-11-11

申请号：US17379703

申请日：2021-07-19

申请人： SK hynix Inc.

发明人： Joo Young LEE

IPC分类号： G06F3/06 ,  G06F8/65

摘要： A memory system and an operating method thereof are disclosed. An operating method of a memory system including a nonvolatile memory device and a controller configured to control the nonvolatile memory device includes the controller updating original data of firmware stored in the nonvolatile memory device, the controller transmitting a notification signal, which notifies a host device of completion of the updating of the original data, to the host device when the updating of the original data is completed, and the controller updating backup data of the firmware stored in the nonvolatile memory device after the notification signal is transmitted.

公开(公告)号：US20210090658A1

公开(公告)日：2021-03-25

申请号：US17115990

申请日：2020-12-09

申请人： SK hynix Inc.

发明人： Hoe Seung JUNG ,  Joo Young LEE

IPC分类号： G11C16/10

摘要： In a memory controller included in a memory system for processing a program operation fail, the memory controller controls a plurality of memory devices commonly coupled to a channel, the plurality of memory devices respectively performing preset program operations, and includes: a buffer memory for storing data to be stored in the plurality of memory devices, based on a buffer memory index; and a program error processor for acquiring fail data corresponding to a program operation fail from a fail memory device and acquiring reprogram data that is data to be stored together with the fail data, based on the buffer memory index.