公开(公告)号：US20210119058A1

公开(公告)日：2021-04-22

申请号：US17114598

申请日：2020-12-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong Ho PARK ,  Wan Don KIM ,  Weon Hong KIM ,  Hyeon Jun BAEK ,  Byoung Hoon LEE ,  Jeong Hyuk YIM ,  Sang Jin HYUN

IPC: H01L29/78 ,  H01L29/49 ,  H01L29/51 ,  H01L27/088

Abstract: A semiconductor device including: a first transistor which include a first gate stack on a substrate; and a second transistor which includes a second gate stack on the substrate, wherein the first gate stack includes a first ferroelectric material layer disposed on the substrate, a first work function layer disposed on the first ferroelectric material layer and a first upper gate electrode disposed on the first work function layer, wherein the second gate stack includes a second ferroelectric material layer disposed on the substrate, a second work function layer disposed on the second ferroelectric material layer and a second upper gate electrode disposed on the second work function layer, wherein the first work function layer includes the same material as the second work function layer, and wherein an effective work function of the first gate stack is different from an effective work function of the second gate stack.

公开(公告)号：US20200013897A1

公开(公告)日：2020-01-09

申请号：US16451787

申请日：2019-06-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JONG HO PARK ,  Wan Don KIM ,  Weon Hong KIM ,  Hyeon Jun BAEK ,  Byoung Hoon LEE ,  Jeong Hyuk YIM ,  Sang Jin HYUN

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/51 ,  H01L29/49

Abstract: A semiconductor device including: a first transistor which include a first gate stack on a substrate; and a second transistor which includes a second gate stack on the substrate, wherein the first gate stack includes a first ferroelectric material layer disposed on the substrate, a first work function layer disposed on the first ferroelectric material layer and a first upper gate electrode disposed on the first work function layer, wherein the second gate stack. includes a second ferroelectric material layer disposed on the substrate, a second work function layer disposed on the second ferroelectric material layer and a second upper gate electrode disposed on the second work function layer, wherein the first work function layer includes the same material as the second work function layer, and wherein an effective work function of the first gate stack is different from an effective work function of the second gate stack.

公开(公告)号：US20230071440A1

公开(公告)日：2023-03-09

申请号：US17737115

申请日：2022-05-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ah Rang CHOI ,  Chan-Sic YOON ,  Jung-Hoon HAN ,  Gyu Hyun KIL ,  Weon Hong KIM ,  Doo San BACK

IPC: H01L27/108

Abstract: Inventive concepts relate to a semiconductor memory device. The semiconductor memory device comprising, a substrate comprising an NMOS region and a PMOS region, a first gate pattern the NMOS region of the substrate, and a second gate pattern disposed on the PMOS region of the substrate. The first gate pattern comprises a first high-k layer, a diffusion mitigation pattern, an N-type work function pattern, and a first gate electrode, which are sequentially stacked on the substrate, the second gate pattern comprises a second high-k layer and a second gate electrode which are sequentially stacked on the substrate, the diffusion mitigation pattern is in contact with the first high-k layer, a stacked structure of the first gate electrode is the same as that of the second gate electrode, and the second gate pattern does not comprise the N-type work function pattern.