公开(公告)号：US20230071440A1

公开(公告)日：2023-03-09

申请号：US17737115

申请日：2022-05-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ah Rang CHOI ,  Chan-Sic YOON ,  Jung-Hoon HAN ,  Gyu Hyun KIL ,  Weon Hong KIM ,  Doo San BACK

IPC: H01L27/108

Abstract: Inventive concepts relate to a semiconductor memory device. The semiconductor memory device comprising, a substrate comprising an NMOS region and a PMOS region, a first gate pattern the NMOS region of the substrate, and a second gate pattern disposed on the PMOS region of the substrate. The first gate pattern comprises a first high-k layer, a diffusion mitigation pattern, an N-type work function pattern, and a first gate electrode, which are sequentially stacked on the substrate, the second gate pattern comprises a second high-k layer and a second gate electrode which are sequentially stacked on the substrate, the diffusion mitigation pattern is in contact with the first high-k layer, a stacked structure of the first gate electrode is the same as that of the second gate electrode, and the second gate pattern does not comprise the N-type work function pattern.