公开(公告)号：US20250022758A1

公开(公告)日：2025-01-16

申请号：US18424111

申请日：2024-01-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongho KIM ,  Sunoo KIM ,  Jinwoo KIM ,  Boin NOH ,  Sejun PARK ,  Jaehee OH

IPC: H01L21/66 ,  H01L23/00

Abstract: A semiconductor device includes a semiconductor substrate, a connection pad disposed on an interlayer insulating layer and electrically connected to an interconnection structure, a passivation layer disposed on the connection pad and having a first opening and a second opening, each exposing at least a portion of the connection pad, a first bump that includes a first lower conductive layer in contact with the connection pad within the first opening and a first upper conductive layer on the first lower conductive layer, and a second bump that includes a second lower conductive layer in contact with the connection pad within the second opening and a second upper conductive layer on the second lower conductive layer. The first and second lower conductive layers include the same material, and the first upper conductive layer and the second upper conductive layer include different materials.

公开(公告)号：US20240275387A1

公开(公告)日：2024-08-15

申请号：US18234517

申请日：2023-08-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Won Ji PARK ,  Sunoo KIM ,  Jaehee OH ,  Hyungwon KIM ,  WooSeong JANG ,  Taekyung KIM ,  Youngbin HYUN

IPC: H03K19/08

CPC classification number: H03K19/08

Abstract: A logic device includes a substrate; at least one first insulating layer on the substrate; a second insulating layer on the at least one first insulating layer; and a capacitor portion in the at least one first insulating layer and the second insulating layer, wherein the at least one first insulating layer includes a plurality of through-holes, the capacitor portion includes a capacitor structure including a lower electrode, a dielectric film, and an upper electrode, and the capacitor structure continuously extends along the inside of the plurality of through-holes and along an upper surface of the at least one first insulating layer around the plurality of through-holes.

公开(公告)号：US20250149478A1

公开(公告)日：2025-05-08

申请号：US18630470

申请日：2024-04-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongho KIM ,  Sunoo KIM ,  Jaehee OH

IPC: H01L23/00

Abstract: A semiconductor package includes: a first substrate that comprises a central area and a peripheral area surrounding the central area; a first pad on the first substrate in the central area; a second pad on the first substrate in the peripheral area; a first solder on and coupled to the first pad; and a second solder on and coupled to the second pad, wherein the first pad has a first recess from a top surface of the first pad, wherein the second pad has a second recess from a top surface of the second pad, wherein a width of the second recess is greater than a width of the first recess, and wherein a volume of the second solder is greater than a volume of the first solder.

公开(公告)号：US20240304504A1

公开(公告)日：2024-09-12

申请号：US18598077

申请日：2024-03-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Boin NOH ,  Yongho KIM ,  Sunoo KIM

IPC: H01L21/66 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L22/32 ,  H01L23/49816 ,  H01L24/08 ,  H01L24/16 ,  H01L25/0652 ,  H01L2224/08146 ,  H01L2224/08155 ,  H01L2224/16146 ,  H01L2224/16157 ,  H01L2924/01029 ,  H01L2924/0665 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311

Abstract: A semiconductor package includes: a semiconductor chip including an active layer; a bump pad positioned on the active layer; a passivation layer covering the bump pad and including a first opening and a second opening, wherein the first opening exposes a first portion of the second surface of the bump pad, and the second opening exposes a second portion of the second surface of the bump pad; a first bump disposed on the first portion of the second surface of the bump pad, which is exposed through the first opening; and a test bump disposed on the second portion of the second surface of the bump pad, which is exposed through the second opening, wherein the first bump includes at least one metal layer, and a length of the test bump in a vertical direction is less than a length of the first bump in the vertical direction.

公开(公告)号：US20240178131A1

公开(公告)日：2024-05-30

申请号：US18382546

申请日：2023-10-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunoo KIM ,  Shaofeng Ding ,  Jeonghoon Ahn ,  Jaehee Oh

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/76813 ,  H01L23/481 ,  H01L23/5283 ,  H01L24/05 ,  H01L2224/05025 ,  H01L2224/05073 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2924/04941

Abstract: A semiconductor device includes: a semiconductor substrate; an integrated circuit layer disposed on the semiconductor substrate; a first metal wiring layer to an n-th metal wiring layer sequentially disposed on the semiconductor substrate and the integrated circuit layer, wherein n is a positive integer; a plurality of wiring vias connecting the first to n-th metal wiring layers to each other, and a through-via extending in a vertical direction from a via connection pad, which is any one of the first metal wiring layer to the n-th metal wiring layer, toward the semiconductor substrate and penetrating the semiconductor substrate, wherein the via connection pad is a capping-type via connection pad formed on an upper surface of the through-via.