公开(公告)号：US20210225429A1

公开(公告)日：2021-07-22

申请号：US16925049

申请日：2020-07-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seongil O ,  Namsung KIM ,  Sukhan LEE

IPC: G11C11/4096 ,  G11C11/4091 ,  G11C11/408 ,  G11C7/10 ,  G06F9/30 ,  G06F9/38

Abstract: A high bandwidth memory and a system having the same are disclosed. The high bandwidth memory includes a buffer die and a plurality of memory dies, each of which includes at least one first processing element bank group and at least one second processing element bank group. The at least one first processing element bank group includes one or more first banks connected to one or more first bank input/output line groups, and a first processing element controller connected to the one or more first bank input/output line groups and a first global input/output line group, and is configured to perform a first processing operation on first data output from one of the one or more first bank input/output line groups and second data transmitted through the first global input/output line group based on a first instruction that is generated based on a first processing command.

公开(公告)号：US20210200696A1

公开(公告)日：2021-07-01

申请号：US16869853

申请日：2020-05-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinhaeng KANG ,  Sukhan LEE

IPC: G06F13/16 ,  G06F13/40

Abstract: A processing in memory (PIM) device includes a memory configured to receive data through a first path from a host processor provided outside the PIM device, and an information gatherer configured to receive the data through a second path connected to the first path when the data is transferred to the memory via the first path, and to generate information by processing the data received through the second path.

公开(公告)号：US20220406369A1

公开(公告)日：2022-12-22

申请号：US17899141

申请日：2022-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngcheon KWON ,  Jaeyoun YOUN ,  Namsung KIM ,  Kyomin SOHN ,  Seongil O ,  Sukhan LEE

IPC: G11C11/406 ,  G11C7/10 ,  G11C11/4076 ,  G11C11/408

Abstract: A memory device including: a plurality of pins for receiving control signals from an external device; a first bank having first memory cells, wherein the first bank is activated in a first operation mode and a second operation mode; a second bank having second memory cells, wherein the second bank is deactivated in the first operation mode and activated in the second operation mode; a processing unit configured to perform an operation on first data, output from the first memory cells, and second data, output from the second memory cells, in the second operation mode; and a processing-in-memory (PIM) mode controller configured to select mode information, indicating one of the first operation mode and the second operation mode, in response to the control signals and to control at least one memory parameter, at least one mode register set (MRS) value, or a refresh mode according to the mode information.

公开(公告)号：US20220068366A1

公开(公告)日：2022-03-03

申请号：US17239854

申请日：2021-04-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngcheon KWON ,  Jaeyoun YOUN ,  Namsung KIM ,  Kyomin SOHN ,  Seongil O ,  Sukhan LEE

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/408 ,  G11C7/10

Abstract: A memory device including: a plurality of pins for receiving control signals from an external device; a first bank having first memory cells, wherein the first bank is activated in a first operation mode and a second operation mode; a second bank having second memory cells, wherein the second bank is deactivated in the first operation mode and activated in the second operation mode; a processing unit configured to perform an operation on first data, output from the first memory cells, and second data, output from the second memory cells, in the second operation mode; and a processing-in-memory (PIM) mode controller configured to select mode information, indicating one of the first operation mode and the second operation mode, in response to the control signals and to control at least one memory parameter, at least one mode register set (MRS) value, or a refresh mode according to the mode information.

公开(公告)号：US20210287735A1

公开(公告)日：2021-09-16

申请号：US17333366

申请日：2021-05-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seongil O ,  Namsung KIM ,  Sukhan LEE

IPC: G11C11/4096 ,  G11C11/408 ,  G06F9/30 ,  G11C7/10 ,  G06F9/38 ,  G11C11/4091

Abstract: A high bandwidth memory and a system having the same are disclosed. The high bandwidth memory includes a buffer die and a plurality of memory dies, each of which includes at least one first processing element bank group and at least one second processing element bank group. The at least one first processing element bank group includes one or more first banks connected to one or more first bank input/output line groups, and a first processing element controller connected to the one or more first bank input/output line groups and a first global input/output line group, and is configured to perform a first processing operation on first data output from one of the one or more first bank input/output line groups and second data transmitted through the first global input/output line group based on a first instruction that is generated based on a first processing command.

公开(公告)号：US20210200513A1

公开(公告)日：2021-07-01

申请号：US16909214

申请日：2020-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinhaeng KANG ,  Sukhan LEE

IPC: G06F7/487 ,  G06F7/544 ,  G06F9/30 ,  G06N3/063

Abstract: A processor-implemented includes receiving a first floating point operand and a second floating point operand, each having an n-bit format comprising a sign field, an exponent field, and a significand field, normalizing a binary value obtained by performing arithmetic operations for fields corresponding to each other in the first and second floating point operands for an n-bit multiplication operation, determining whether the normalized binary value is a number that is representable in the n-bit format or an extended normal number that is not representable in the n-bit format, according to a result of the determining, encoding the normalized binary value using an extension bit format in which an extension pin identifying whether the normalized binary value is the extended normal number is added to the n-bit format, and outputting the encoded binary value using the extended bit format, as a result of the n-bit multiplication operation.

公开(公告)号：US20240370227A1

公开(公告)日：2024-11-07

申请号：US18774303

申请日：2024-07-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinhaeng KANG ,  Sukhan LEE

IPC: G06F7/487 ,  G06F5/01 ,  G06F7/544 ,  G06F9/30

Abstract: A processor-implemented includes receiving a first floating point operand and a second floating point operand, each having an n-bit format comprising a sign field, an exponent field, and a significand field, normalizing a binary value obtained by performing arithmetic operations for fields corresponding to each other in the first and second floating point operands for an n-bit multiplication operation, determining whether the normalized binary value is a number that is representable in the n-bit format or an extended normal number that is not representable in the n-bit format, according to a result of the determining, encoding the normalized binary value using an extension bit format in which an extension pin identifying whether the normalized binary value is the extended normal number is added to the n-bit format, and outputting the encoded binary value using the extended bit format, as a result of the n-bit multiplication operation.

公开(公告)号：US20230094148A1

公开(公告)日：2023-03-30

申请号：US17879523

申请日：2022-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sukhan LEE ,  Shinhaeng KANG ,  Kyomin SOHN

IPC: G06F3/06

Abstract: A memory device for reducing timing parameters and power consumption for an internal processing operation and a method of implementing the same are provided. The memory device includes a memory cell array, a processing-in-memory (PIM) circuit configured to perform a processing operation and a control logic circuit configured to control a normal mode and an internal processing mode. The control logic circuit writes an operation result obtained by the processing operation of the PIM circuit in the internal processing mode in the memory cell array and provides read data read from the memory cell array to the PIM circuit.

公开(公告)号：US20230042954A1

公开(公告)日：2023-02-09

申请号：US17965351

申请日：2022-10-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinhaeng KANG ,  Sukhan LEE

IPC: G06F7/487 ,  G06F7/544 ,  G06F9/30 ,  G06F5/01

Abstract: A processor-implemented includes receiving a first floating point operand and a second floating point operand, each having an n-bit format comprising a sign field, an exponent field, and a significand field, normalizing a binary value obtained by performing arithmetic operations for fields corresponding to each other in the first and second floating point operands for an n-bit multiplication operation, determining whether the normalized binary value is a number that is representable in the n-bit format or an extended normal number that is not representable in the n-bit format, according to a result of the determining, encoding the normalized binary value using an extension bit format in which an extension pin identifying whether the normalized binary value is the extended normal number is added to the n-bit format, and outputting the encoded binary value using the extended bit format, as a result of the n-bit multiplication operation.

公开(公告)号：US20220318165A1

公开(公告)日：2022-10-06

申请号：US17845441

申请日：2022-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinhaeng KANG ,  Sukhan LEE

IPC: G06F13/16 ,  G06F13/40 ,  G06F3/06

Abstract: A processing in memory (PIM) device includes a memory configured to receive data through a first path from a host processor provided outside the PIM device, and an information gatherer configured to receive the data through a second path connected to the first path when the data is transferred to the memory via the first path, and to generate information by processing the data received through the second path.