公开(公告)号：US20250062210A1

公开(公告)日：2025-02-20

申请号：US18433887

申请日：2024-02-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongyo Kim ,  Minsoo Kim ,  Sang-Sick Park

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065

Abstract: A semiconductor package includes a first semiconductor die; a second semiconductor die on the first semiconductor die; and an underfill layer between the first semiconductor die and the second semiconductor die, where the first semiconductor die includes: a first substrate including a main region and first corner regions that are adjacent to respective corners of the second semiconductor die, and where the main region overlaps a center of the second semiconductor die; redistribution patterns that are on the first substrate and include dummy wirings and signal wirings; a redistribution insulating layer on the redistribution patterns; and conductive pads that are on the redistribution insulating layer and include dummy pads and signal pads, where a pattern density of a first set of the conductive pads on the first corner regions is greater than a pattern density of a second set of the conductive pads on the main region.

公开(公告)号：US20240186289A1

公开(公告)日：2024-06-06

申请号：US18226990

申请日：2023-07-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hanmin Lee ,  Unbyoung Kang ,  Seongyo Kim ,  Sangsick Park

IPC: H01L25/065 ,  H01L21/461 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H10B80/00

CPC classification number: H01L25/0657 ,  H01L21/461 ,  H01L21/563 ,  H01L23/3114 ,  H01L24/16 ,  H01L24/32 ,  H01L25/50 ,  H10B80/00 ,  H01L2224/16145 ,  H01L2224/32145

Abstract: A method of manufacturing a semiconductor package comprises stacking, via an adhesive member, a plurality of memory dies to form a memory die stack on a buffer die; forming a first molding member on the buffer die to cover the memory die stack; polishing an upper surface of the first molding member to expose an upper surface of an uppermost memory die in the memory die stack, the uppermost memory die positioned in an uppermost layer in the memory die stack; removing edge portions of the uppermost memory die together with at least a portion of the first molding member and at least a portion of the adhesive member to form a stepped portion; and forming a second molding member on the first molding member to cover the stepped portion of the uppermost memory die.

公开(公告)号：US20240128221A1

公开(公告)日：2024-04-18

申请号：US18367642

申请日：2023-09-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minsoo Kim ,  Seongyo Kim ,  Sangsick Park ,  Soyoun Lee

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L24/27 ,  H01L2224/16148 ,  H01L2224/278 ,  H01L2224/29018 ,  H01L2224/29552 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/381

Abstract: According to embodiments of the present disclosure, a semiconductor package is provided. The semiconductor package includes a substrate including a first surface and a second surface opposite to the first surface; and a plurality of lower pads on the second surface at different intervals. The semiconductor package further includes: a plurality of bumps attached to the plurality of lower pads; a first non-conductive film on the second surface of the substrate; and a second non-conductive film on the first non-conductive film. A plurality of regions are defined in the semiconductor package according to a separation distance between the plurality of bumps, such that each region of the plurality of regions includes respective bumps, from among the plurality of bumps, that have a respective separation distance between neighboring ones of the respective bumps within the region. A sum of thicknesses of the first and second non-conductive films is constant.