公开(公告)号：US12238195B2

公开(公告)日：2025-02-25

申请号：US18059522

申请日：2022-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin Kim ,  Seongyoung Ryu ,  Soojoo Lee ,  Sengsub Chun ,  Hyunwoo Cho ,  Jongil Hwang

IPC: H04L7/00 ,  G06F1/08 ,  G09G5/00 ,  H03K19/20

Abstract: A receiver circuit includes data lane modules, a clock lane module, a bias current controller and a link layer. Each of the data lane modules receive respective data signals. The clock lane module receives clock signals and provides each of the data lane modules with a respective divided clock signal among divided clock signals. The bias current controller controls a clock bias current. The link layer provides a bias control signal to the bias current controller and provides clock gating signals to the clock lane module, based on low power data signals and low power clock signals. The bias current controller, based on the bias control signal, provides the clock bias current having a first magnitude to the clock lane module in a second power mode and provides the clock bias current having a second magnitude to the clock lane module in a third power mode.

公开(公告)号：US20230179394A1

公开(公告)日：2023-06-08

申请号：US18059522

申请日：2022-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin KIM ,  Seongyoung Ryu ,  Soojoo Lee ,  Sengsub Chun ,  Hyunwoo Cho ,  Jongil Hwang

IPC: H04L7/00 ,  G06F1/08

CPC classification number: H04L7/0079 ,  H04L7/0008 ,  G06F1/08 ,  H03K19/20

Abstract: A receiver circuit includes data lane modules, a clock lane module, a bias current controller and a link layer. Each of the data lane modules receive respective data signals. The clock lane module receives clock signals and provides each of the data lane modules with a respective divided clock signal among divided clock signals. The bias current controller controls a clock bias current. The link layer provides a bias control signal to the bias current controller and provides clock gating signals to the clock lane module, based on low power data signals low power clock signals. The bias current controller, based on the bias control signal, provides the clock bias current having a first magnitude to the clock lane module in a second power mode and provides the clock bias current having a second magnitude to the clock lane module in a third power mode.

公开(公告)号：US11223468B1

公开(公告)日：2022-01-11

申请号：US17194831

申请日：2021-03-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungho Ryu ,  Kyongho Kim ,  Kilhoon Lee ,  Yeongcheol Rhee ,  Taeho Lee ,  Hyunwook Lim ,  Younghwan Chang ,  Sengsub Chun

IPC: H04L7/00 ,  H04L27/01

Abstract: A receiver circuit includes an equalizer configured to generate an equalization signal by equalizing an input data signal transferred through a communication channel based on an equalization coefficient; a clock data recovery circuit configured to generate a data clock signal and an edge clock signal based on the equalization signal, generate a data sample signal including a plurality of data bits by sampling the equalization signal in synchronization with the data clock signal, and generate an edge sample signal including a plurality of edge bits by sampling the equalization signal in synchronization with the edge clock signal; and an equalization control circuit configured to control the equalization coefficient by comparing the plurality of data bits and the plurality of edge bits.