公开(公告)号：US11223468B1

公开(公告)日：2022-01-11

申请号：US17194831

申请日：2021-03-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungho Ryu ,  Kyongho Kim ,  Kilhoon Lee ,  Yeongcheol Rhee ,  Taeho Lee ,  Hyunwook Lim ,  Younghwan Chang ,  Sengsub Chun

IPC: H04L7/00 ,  H04L27/01

Abstract: A receiver circuit includes an equalizer configured to generate an equalization signal by equalizing an input data signal transferred through a communication channel based on an equalization coefficient; a clock data recovery circuit configured to generate a data clock signal and an edge clock signal based on the equalization signal, generate a data sample signal including a plurality of data bits by sampling the equalization signal in synchronization with the data clock signal, and generate an edge sample signal including a plurality of edge bits by sampling the equalization signal in synchronization with the edge clock signal; and an equalization control circuit configured to control the equalization coefficient by comparing the plurality of data bits and the plurality of edge bits.

公开(公告)号：US11569773B2

公开(公告)日：2023-01-31

申请号：US16922419

申请日：2020-07-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taeho Lee ,  Junghyun Lee ,  Junghoon Lee ,  Yoonsup Kim ,  Youngjae Park ,  Jieun Ban ,  Jong-Hyun Shin

IPC: H02P27/08 ,  H02M5/458 ,  F04D13/06

Abstract: A compressor control apparatus includes a rectifier configured to rectify AC power to DC power; an inverter including a plurality of switching elements, configured to convert the DC power into a three-phase voltage according to a pulse width modulation (PWM) signal applied to the plurality of switching elements; a motor configured to receive a three-phase current based on the three-phase voltage; a current detector configured to detect a sum of a first phase current, a second phase current, and a third phase current supplied to the motor; and a controller configured to differently determine a duty ratio of the PWM signal applied to each of the plurality of switching elements, and to determine the first phase current, the second phase current, and the third phase current, respectively, based on the determined duty ratio and the sum of the currents detected from the current detector.

公开(公告)号：US11996065B2

公开(公告)日：2024-05-28

申请号：US17985599

申请日：2022-11-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungho Ryu ,  Kyongho Kim ,  Yongyun Park ,  Kilhoon Lee ,  Yeongcheol Rhee ,  Taeho Lee ,  Hyunwook Lim

IPC: G09G5/00

CPC classification number: G09G5/008 ,  G09G2370/04

Abstract: Provided is a display driving circuit. The display driving circuit includes a clock data recovery circuit configured to receive a data signal and generate a clock signal and a first output data signal, an eye margin test circuit configured to sample the data signal by using the clock signal, based on a vertical measurement voltage and generate a second output data signal, and a bit error check circuit configured to measure a bit error rate of the data signal, based on the first output data signal and the second output data signal, wherein the clock data recovery circuit includes a jitter generator configured to generate jitter of the clock signal such that a jitter amplitude varies according to a horizontal control signal.