公开(公告)号：US20170069737A1

公开(公告)日：2017-03-09

申请号：US15236726

申请日：2016-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-In CHOI ,  Bong-Soo KIM ,  Hyun-Seung KIM ,  Hyun-Gi HONG

IPC: H01L29/66 ,  H01L29/08 ,  H01L21/02 ,  H01L21/225

CPC classification number: H01L29/66803 ,  H01L21/02175 ,  H01L21/02244 ,  H01L21/02252 ,  H01L21/2255 ,  H01L21/2256 ,  H01L29/0847 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: Provided are a semiconductor device and a method of fabricating the same. The method comprises forming an active fin extending along a first direction; forming a field insulating layer exposing an upper part of the active fin, along long sides of the active fin; forming a dummy gate pattern extending along a second direction intersecting the first direction, on the active fin; forming a spacer on at least one side of the dummy gate pattern; forming a liner layer covering the active fin exposed by the spacer and the dummy gate pattern; forming a dopant supply layer containing a dopant element, on the liner layer; and forming a doped region in the active fin along an upper surface of the active fin by heat-treating the dopant supply layer.

Abstract translation: 提供半导体器件及其制造方法。 该方法包括形成沿着第一方向延伸的活性翅片; 形成沿有源鳍片的长边暴露活性鳍片的上部的场绝缘层; 在所述活动翅片上形成沿着与所述第一方向相交的第二方向延伸的虚拟栅极图案; 在所述伪栅极图案的至少一侧上形成间隔物; 形成覆盖由所述间隔物和所述伪栅极图案露出的所述有源鳍的衬垫层; 在所述衬垫层上形成含有掺杂剂元素的掺杂剂供给层; 以及通过热处理所述掺杂剂供应层，沿着所述活性鳍片的上表面在所述活性鳍片中形成掺杂区域。

公开(公告)号：US20190164776A1

公开(公告)日：2019-05-30

申请号：US16123262

申请日：2018-09-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung-In CHOI ,  Sang-Hoon HAN ,  Sun-Jung KIM ,  Tae-Gon KIM ,  Hyun-Chul SONG

IPC: H01L21/3115 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/265 ,  H01L21/02

Abstract: A method of manufacturing a semiconductor device, the method including forming dummy gate structures on a substrate; forming spacers on sidewalls of the dummy gate structures; forming a preliminary first interlayer insulation pattern to fill a gap between adjacent spacers; etching an upper portion of the preliminary first interlayer insulation pattern through a first etching process to form a preliminary second interlayer insulation pattern; implanting an ion on the dummy gate structures, the spacers, and the preliminary second interlayer insulation pattern through an ion-implanting process; etching an upper portion of the preliminary second interlayer insulation pattern through a second etching process to form an interlayer insulation pattern having a flat upper surface; and forming a capping pattern on the interlayer insulation pattern to fill a gap between the spacers.