公开(公告)号：US09897753B2

公开(公告)日：2018-02-20

申请号：US15388951

申请日：2016-12-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Kwon Bok ,  Kyoung-Ho Ha ,  Dong-Jae Shin ,  Seong-Gu Kim ,  Kwan-Sik Cho ,  Beom-Suk Lee ,  Jung-Ho Cha ,  Hyun-Il Byun ,  Dong-Hyun Kim ,  Yong-Hwack Shin ,  Jung-Hye Kim

IPC: G02B6/12 ,  G02B6/122 ,  G02B6/125 ,  G02B6/136

CPC classification number: G02B6/1228 ,  G02B6/125 ,  G02B6/136 ,  G02B2006/12097

Abstract: An optical device includes a substrate; a trench in a portion of the substrate; a clad layer arranged in the trench; a first structure arranged on the clad layer to have a first depth; and a second structure arranged on the clad layer to have a second depth different from the first depth.

公开(公告)号：US09786600B2

公开(公告)日：2017-10-10

申请号：US14970160

申请日：2015-12-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Il Cho ,  Nam-Gun Kim ,  Jin-Young Kim ,  Hyun-Chul Yoon ,  Bong-Soo Kim ,  Kwan-Sik Cho

IPC: H01L27/00 ,  H01L29/00 ,  H01L23/00 ,  H01L23/528 ,  H01L29/423 ,  H01L29/78 ,  H01L27/105 ,  H01L29/45 ,  H01L23/535 ,  H01L29/06 ,  H01L27/108

CPC classification number: H01L23/528 ,  H01L23/535 ,  H01L27/1052 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/0649 ,  H01L29/42324 ,  H01L29/45 ,  H01L29/78 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.