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    MEMORY DEVICE, MEMORY SYSTEM INCLUDING MEMORY DEVICE, AND OPERATING METHOD OF MEMORY DEVICE
    1.
    发明申请
    MEMORY DEVICE, MEMORY SYSTEM INCLUDING MEMORY DEVICE, AND OPERATING METHOD OF MEMORY DEVICE 有权

    公开(公告)号：US20250156310A1

    公开(公告)日：2025-05-15

    申请号：US18946517

    申请日：2024-11-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junha LEE ,  Kyoungtae KANG ,  Hyunsuk KANG ,  Dongho SHIN ,  Kang Yoon LEE

    IPC: G06F12/02 ,  G06F13/40

    Abstract: A memory device includes data pads that are connected to an external memory controller, a ZQ pad that is connected to an external resistor, data drivers and receivers that are connected to the data pads and output first data signals to the data pads or receive second data signals from the data pads, and a ZQ calibrator that is connected to the ZQ pad. The memory device performs ZQ calibration based on a voltage of the ZQ pad, generates ZQ codes as a result of the ZQ calibration, and provides the ZQ codes to the data drivers and receivers. The ZQ calibrator performs a first-type ZQ calibration in response to a command received from the external memory controller and performs a second-type ZQ calibration without the command being received from the external memory controller.

    DUTY CYCLE CORRECTORS AND METHODS OF OPERATING THE SAME
    4.
    发明申请
    DUTY CYCLE CORRECTORS AND METHODS OF OPERATING THE SAME 审中-公开

    公开(公告)号：US20190165774A1

    公开(公告)日：2019-05-30

    申请号：US16006107

    申请日：2018-06-12

    Applicant: Samsung Electronics Co., Ltd. ,  Research & Business Foundation SUNGKYUNKWAN UNIVERSITY

    Inventor： KYOUNGTAE KANG ,  Kang Yoon LEE

    IPC: H03K5/156 ,  H03K5/133

    Abstract: A duty cycle corrector includes a delay chain, an edge detector, a falling edge shift (FES) controller, a plurality of falling edge modulator (FEM) cores, and a phase interpolator. The delay chain delays a first clock to generate a delay clock, and generates first and second sampling control signals. The edge detector samples the first clock and a second clock using the first and second sampling control signals to obtain first and second sampling signals. The FES controller determines a modulation direction and a modulation width based on the first and second sampling signals. The plurality of FEM cores first modulate the first edge of the first clock and second modulate the first edge of the delay clock using the modulation direction and the modulation width. The phase interpolator performs phase interpolation on the results of the first and second modulations.

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