Reconfigurable processor for parallel processing and operation method of the reconfigurable processor
    1.
    发明授权
    Reconfigurable processor for parallel processing and operation method of the reconfigurable processor 有权
    可重构处理器,用于可重构处理器的并行处理和操作方法

    公开(公告)号:US09558003B2

    公开(公告)日:2017-01-31

    申请号:US14092060

    申请日:2013-11-27

    Abstract: A reconfigurable processor and an operation method of the reconfigurable processor may include: a status register configured to store a status value used to determine at least one execution mode in a processor; a parallel processing scheduler configured to schedule at least one of a very long instruction word (VLIW) logic and a coarse grained architecture (CGA) logic to be used based on the stored status value; a VLIW register configured to store processed data according to the VLIW logic; and a CGA register configured to store processed data according to the CGA logic.

    Abstract translation: 可重构处理器和可重构处理器的操作方法可以包括:状态寄存器,被配置为存储用于在处理器中确定至少一个执行模式的状态值; 配置为基于所存储的状态值来调度要使用的非常长的指令字(VLIW)逻辑和粗粒度体系结构(CGA)逻辑中的至少一个的并行处理调度器; VLIW寄存器,被配置为根据VLIW逻辑来存储处理的数据; 以及CGA寄存器,被配置为根据CGA逻辑来存储处理的数据。

    Arithmetic processing apparatus and method for high speed processing of application
    2.
    发明授权
    Arithmetic processing apparatus and method for high speed processing of application 有权
    用于高速处理应用的算术处理装置和方法

    公开(公告)号:US09471309B2

    公开(公告)日:2016-10-18

    申请号:US13945267

    申请日:2013-07-18

    CPC classification number: G06F9/3001 G06F9/544

    Abstract: An arithmetic processing apparatus and method for high speed processing of an application are provided. The arithmetic processing apparatus may include a program control unit to store operation processing information necessary for application operation in a communication channel by executing an application code, and an operation processing unit to process the application operation using the operation processing information stored in the communication channel.

    Abstract translation: 提供了一种用于应用程序的高速处理的算术处理装置和方法。 算术处理装置可以包括:程序控制单元,其通过执行应用代码来存储通信信道中的应用操作所需的操作处理信息;以及操作处理单元,使用存储在通信信道中的操作处理信息来处理应用操​​作。

    APPARATUS AND METHOD FOR IN-LOOP FILTERING BASED ON LARGEST CODING UNIT FOR REDUCING EXTERNAL MEMORY ACCESS BANDWIDTH
    5.
    发明申请
    APPARATUS AND METHOD FOR IN-LOOP FILTERING BASED ON LARGEST CODING UNIT FOR REDUCING EXTERNAL MEMORY ACCESS BANDWIDTH 审中-公开
    用于减少外部存储器访问带宽的最大编码单元进行环路滤波的装置和方法

    公开(公告)号:US20140286442A1

    公开(公告)日:2014-09-25

    申请号:US14079071

    申请日:2013-11-13

    CPC classification number: H04N19/86 H04N19/423 H04N19/82

    Abstract: An apparatus and method for in-loop filtering based on a largest coding unit (LCU) to reduce an external memory access bandwidth. An in-loop filter may include an external memory to store decoded frames, an internal memory to store pixels in use for deblocking filtering and sample adaptive offset filtering, a horizontal deblocking filter to perform deblocking filtering on input pixels in a horizontal direction with respect to vertical edge boundaries within an input area, a vertical deblocking filter to perform deblocking filtering in a vertical direction with respect to horizontal edge boundaries within the input area, and a sample adaptive offset filter to perform sample adaptive offset filtering.

    Abstract translation: 一种用于基于最大编码单元(LCU)进行环路滤波的装置和方法,以减少外部存储器存取带宽。 环路滤波器可以包括用于存储解码帧的外部存储器,用于存储用于去块滤波和采样自适应偏移滤波的像素的内部存储器,水平去块滤波器,用于对水平方向上的输入像素执行去块滤波,相对于 在输入区域内的垂直边缘边界,相对于输入区域内的水平边界边界在垂直方向上执行去块滤波的垂直去块滤波器,以及采样自适应偏移滤波器,以执行采样自适应偏移滤波。

    RECONFIGURABLE PROCESSOR FOR PARALLEL PROCESSING AND OPERATION METHOD OF THE RECONFIGURABLE PROCESSOR
    6.
    发明申请
    RECONFIGURABLE PROCESSOR FOR PARALLEL PROCESSING AND OPERATION METHOD OF THE RECONFIGURABLE PROCESSOR 有权
    可重构加工器的并行处理和操作方法的可重构处理器

    公开(公告)号:US20140149714A1

    公开(公告)日:2014-05-29

    申请号:US14092060

    申请日:2013-11-27

    Abstract: A reconfigurable processor and an operation method of the reconfigurable processor may include: a status register configured to store a status value used to determine at least one execution mode in a processor; a parallel processing scheduler configured to schedule at least one of a very long instruction word (VLIW) logic and a coarse grained architecture (CGA) logic to be used based on the stored status value; a VLIW register configured to store processed data according to the VLIW logic; and a CGA register configured to store processed data according to the CGA logic.

    Abstract translation: 可重构处理器和可重构处理器的操作方法可以包括:状态寄存器,被配置为存储用于在处理器中确定至少一个执行模式的状态值; 配置为基于所存储的状态值来调度要使用的非常长的指令字(VLIW)逻辑和粗粒度体系结构(CGA)逻辑中的至少一个的并行处理调度器; VLIW寄存器,被配置为根据VLIW逻辑来存储处理的数据; 以及CGA寄存器,被配置为根据CGA逻辑来存储处理的数据。

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