公开(公告)号：US20240404931A1

公开(公告)日：2024-12-05

申请号：US18436993

申请日：2024-02-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyejin LEE ,  Jihye SHIN ,  Kihyun KIM

IPC: H01L23/498 ,  H01L21/027 ,  H01L21/311 ,  H01L23/00 ,  H01L25/065 ,  H10B80/00

Abstract: A method includes: forming a first photoresist layer on a first insulating layer; forming a first photoresist pattern having first opening patterns using a first exposure mask; etching the first insulating layer using the first photoresist pattern to form first via holes; removing the first photoresist pattern; forming a second photoresist layer on the first insulating layer; forming a second photoresist pattern having second opening patterns using a second exposure mask; etching the first insulating layer using the second photoresist pattern to form second via holes; removing the first photoresist pattern; forming a redistribution wiring layer on the first insulating layer, the redistribution wiring layer having first redistribution wirings connected to first bonding pads under the first insulating layer through the via holes; and mounting a semiconductor chip on the redistribution wiring layer, the semiconductor chip comprising chip pads connected to the first redistribution wirings.

公开(公告)号：US20230142301A1

公开(公告)日：2023-05-11

申请号：US18053806

申请日：2022-11-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changbo LEE ,  Joonseok OH ,  Youngmin KIM ,  Jihye SHIN ,  Hyundong LEE

IPC: H01L23/498 ,  H01L25/10 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L23/49894 ,  H01L24/16 ,  H01L25/105 ,  H01L23/49816 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/182 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/18301

Abstract: A semiconductor package includes a first redistribution structure including a plurality of first redistribution layers and a plurality of first redistribution vias. A semiconductor chip is on the first redistribution structure. The semiconductor chip includes a chip pad. A connection pad is between the first redistribution structure and the semiconductor chip, and is connected to the first redistribution structure. A connection bump is connected to the connection pad and the chip pad. A molding layer extends around the first redistribution structure and the semiconductor chip, and a through electrode extends through the molding layer. A wetting layer is between the first redistribution structure and the molding layer.