公开(公告)号：US20230269933A1

公开(公告)日：2023-08-24

申请号：US18049839

申请日：2022-10-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaepil LEE ,  Minhee Cho

IPC: H01L27/108 ,  H01L29/08 ,  H01L29/24

CPC classification number: H01L27/10814 ,  H01L29/0847 ,  H01L29/24

Abstract: A transistor structure including an active pattern defined by a first isolation pattern on a substrate, a second isolation pattern at an upper portion of the active pattern, a gate structure extending through the active pattern and the first isolation pattern, at least a lower portion of the gate structure extending through the second isolation pattern, a first oxide semiconductor pattern on a lower surface and a sidewall of the gate structure, the first oxide semiconductor pattern including In-rich IGZO and at least partially contacting the first and second isolation patterns, and source/drain regions at upper portions of the active pattern adjacent to the gate structure may be provided.

公开(公告)号：US20230337418A1

公开(公告)日：2023-10-19

申请号：US18211807

申请日：2023-06-20

Applicant: Samsung Electronics CO., LTD.

Inventor： Jaepil LEE ,  Chulkwon Park

IPC: H10B12/00 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4091

CPC classification number: H10B12/50 ,  H10B12/315 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4087 ,  G11C11/4091

Abstract: A memory core circuit includes a memory cell array including sub cell arrays and a core control circuit, which includes sub peripheral circuits that are disposed under each sub cell array. Each sub peripheral circuit includes a sense amplifier region, which includes a plurality of bitline sense amplifiers, and a rest circuit region, which includes other circuits. First-type bitline sense amplifiers, which are connected to first-type bitlines, are disposed in the sense amplifier region of each sub peripheral circuit, and the first-type bitlines are disposed above the sense amplifier region of each sub peripheral circuit. Second-type bitline sense amplifiers, which are connected to second-type bitlines, are disposed in the sense amplifier region of a neighboring sub peripheral circuit adjacent in the column direction to a first sub peripheral circuit of the sub peripheral circuit, and the second-type bitlines are disposed above the rest region of each sub peripheral circuit.

公开(公告)号：US20230232614A1

公开(公告)日：2023-07-20

申请号：US18095041

申请日：2023-01-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaepil LEE ,  Hijung KIM

IPC: H10B12/00

CPC classification number: H10B12/34 ,  H10B12/485 ,  H10B12/053

Abstract: A semiconductor device includes a semiconductor substrate, an active region on the semiconductor substrate and including a first semiconductor material, an isolation layer on the semiconductor substrate and a side surface of the active region, a first gate structure in a first gate trench crossing the active region, a second gate structure in a second gate trench in the isolation layer, the second gate structure being parallel to the first gate structure and adjacent to the active region, a semiconductor layer covering at least a part of the side surface of the active region, the semiconductor layer including a second semiconductor material different from the first semiconductor material, and at least a part of the semiconductor layer being between the active region and the second gate structure, and source/drain regions in the active region on opposite sides of the first gate trench.