公开(公告)号：US09496863B2

公开(公告)日：2016-11-15

申请号：US14616824

申请日：2015-02-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Han Jeon

IPC: H03K17/16 ,  H03K17/687 ,  G05F1/46

CPC classification number: H03K17/165 ,  G05F1/465 ,  H03K17/6871

Abstract: A power gating circuit in an integrated circuit, including a circuit block coupled to a virtual power supply line, includes a first transistor and a buffer. The first transistor is coupled between a first power supply line and the virtual power supply line, and has a body coupled to the first power supply line. The buffer buffers a control signal to apply the buffered control signal to the first transistor, and includes a second transistor having a source coupled to a second power supply line and a body coupled to the first power supply line.

Abstract translation: 集成电路中的电源门控电路，包括耦合到虚拟电源线的电路块，包括第一晶体管和缓冲器。 第一晶体管耦合在第一电源线和虚拟电源线之间，并且具有耦合到第一电源线的主体。 缓冲器缓冲控制信号以将缓冲的控制信号施加到第一晶体管，并且包括具有耦合到第二电源线的源极和耦合到第一电源线的主体的第二晶体管。

公开(公告)号：US10026471B2

公开(公告)日：2018-07-17

申请号：US15009149

申请日：2016-01-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： In-Sub Shin ,  Jae-Han Jeon ,  Hyung-Ock Kim

IPC: G11C5/14 ,  G11C11/417 ,  G11C7/10

Abstract: A system-on-chip and an electronic device including the system-on-chip are provided. The system-on-chip includes a power switch, a logic block, a memory device, and a buffer. The power switch is coupled between a first power supply line and a virtual power supply line, and turns on in response to a switch control signal. The logic block is coupled between the virtual power supply line and a ground line. The memory device is coupled between a second power supply line and the ground line. The buffer is coupled between the second power supply line and the ground line, and generates the switch control signal based on a sleep signal.