公开(公告)号：US11990080B2

公开(公告)日：2024-05-21

申请号：US18091155

申请日：2022-12-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hojin Kim ,  Donghyun Yeom ,  Jaehun Cho

IPC: G06F9/50 ,  G06F9/48 ,  G09G3/20 ,  G09G5/10

CPC classification number: G09G3/2092 ,  G09G2340/0407 ,  G09G2354/00 ,  G09G2380/02

Abstract: An electronic device includes: a display panel, a display driving circuit, and at least one processor operatively connected to the display driving circuit. The at least one processor may be configured to: determine a resolution of each of a plurality of applications, and generate a frame image including regions corresponding to execution screens of the plurality of applications and determined resolutions of the plurality of applications, based at least partially on the resolutions of the plurality of applications and/or information on a display region corresponding to the execution screens of the plurality of applications on the display panel, and transmit, to the display driving circuit, the frame image and coordinate information of each of the regions included in the frame image. The display driving circuit up-scales at least a portion, which has resolution lower than resolution of the display panel, of the regions included in the frame image, based on the frame image and the coordinate information of each of the regions, such that the frame image has resolution corresponding to the resolution of the display panel and control the display panel to display the execution screen of each of the plurality of applications, based on the up-scaled frame image.

公开(公告)号：US20220255549A1

公开(公告)日：2022-08-11

申请号：US17646767

申请日：2022-01-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gurnrack Moon ,  Younggwan Kim ,  Hojin Kim

IPC: H03K19/017 ,  H03K19/17784 ,  H03K19/17736 ,  H03K19/17728

Abstract: The present disclosure provides an integrated circuit and a computing system. The integrated circuit and a computing system includes a dynamic voltage and frequency scaling (DVFS) operation and a method of operating the integrated circuit. The integrated circuit includes a plurality of sub blocks and a dynamic voltage and frequency scaling (DVFS) controller. The DVFS controller is configured to output a workload of the plurality of sub blocks, determine a first frequency corresponding to the workload, determine a first voltage corresponding to the first frequency, and provide a second frequency among at least one frequency corresponding to the first voltage to the plurality of sub blocks.

公开(公告)号：US11538438B2

公开(公告)日：2022-12-27

申请号：US17277539

申请日：2019-09-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongkon Bae ,  Hojin Kim ,  Yohan Lee ,  Yunpyo Hong ,  Donghui Kim ,  Eunsook Seo ,  Dongkyoon Han

IPC: G06F3/038 ,  G09G5/00 ,  G09G5/12 ,  G09G5/22

Abstract: An electronic device according to various embodiments may include a display panel, a Display Driving Integrated Circuit (DDIC) operatively coupled to the display panel, and a processor operatively coupled to the DDIC. The DDIC may be configured to receive, from the processor, a signal indicating that a first resolution is to be converted to a second resolution while displaying an image at the first resolution through the display panel, based on a horizontal synchronization signal including a first porch interval, change a length of the porch interval in response to the reception, and display the image at the second resolution through the display panel, based on the horizontal synchronization signal including the porch interval having the changed length.

公开(公告)号：US12021523B2

公开(公告)日：2024-06-25

申请号：US17646767

申请日：2022-01-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gurnrack Moon ,  Younggwan Kim ,  Hojin Kim

IPC: H03K19/017 ,  G06F1/08 ,  G06F1/324 ,  G06F1/3296 ,  G06F11/30 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17784

CPC classification number: H03K19/01728 ,  G06F1/08 ,  G06F1/324 ,  H03K19/17728 ,  H03K19/1774 ,  H03K19/17784

Abstract: The present disclosure provides an integrated circuit and a computing system. The integrated circuit and a computing system includes a dynamic voltage and frequency scaling (DVFS) operation and a method of operating the integrated circuit. The integrated circuit includes a plurality of sub blocks and a dynamic voltage and frequency scaling (DVFS) controller. The DVFS controller is configured to output a workload of the plurality of sub blocks, determine a first frequency corresponding to the workload, determine a first voltage corresponding to the first frequency, and provide a second frequency among at least one frequency corresponding to the first voltage to the plurality of sub blocks.

公开(公告)号：US11631382B2

公开(公告)日：2023-04-18

申请号：US17282270

申请日：2019-11-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongkon Bae ,  Hanyuool Kim ,  Donghwy Kim ,  Hojin Kim ,  Hyunjun Park ,  Yohan Lee ,  Hongkook Lee ,  Dongkyoon Han ,  Yunpyo Hong

IPC: G09G5/38 ,  G09G3/00

Abstract: An electronic device is disclosed that includes a display, a display driver IC that drives the display, and at least one processor operationally connected with the display and the display driver IC. The display driver IC moves a display location of one or more pixel data corresponding to an image associated with at least one application from a specified point by a specified distance on an active area of the display. The at least one processor is configured to scale up a first portion of the image by a specified range based on the specified distance, scale down a second portion of the image by the specified range based on the specified distance, and display the image on the active area based on the scaled-up first portion or the scaled-down second portion. In addition, various embodiments recognized through the specification are possible.

公开(公告)号：US20220308920A1

公开(公告)日：2022-09-29

申请号：US17529854

申请日：2021-11-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seyeong Byeon ,  Jonglae Park ,  Hojin Kim ,  Gurnrack Moon ,  Daeyeong Lee ,  Youngtae Lee

IPC: G06F9/48

Abstract: A task scheduling method for a central processing unit (CPU) including a plurality of cores includes receiving a task processing request, obtaining first feedback data for the plurality of cores, obtaining second feedback data for an external intellectual property (IP) block outside the CPU, and assigning a task to at least one of the plurality of cores based on the first feedback data and the second feedback data.