公开(公告)号：US20160034094A1

公开(公告)日：2016-02-04

申请号：US14807530

申请日：2015-07-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Hyub Kang ,  Ki-Duk Kim ,  Jun-Chul Park ,  Ho-Jin Park ,  Kyung-Hoon Lee ,  Min-Chul Lee ,  Jin-Chul Lee ,  Choong-Hoon Lee ,  Michael Choi ,  Yoon-Kyung Choi

IPC: G06F3/041 ,  H03F3/45 ,  H03G3/00

CPC classification number: G06F3/0416 ,  H03F3/45475 ,  H03F3/45968 ,  H03F2200/228 ,  H03F2203/45116 ,  H03F2203/45522 ,  H03F2203/45591 ,  H03G1/0088

Abstract: A programmable gain amplifier (PGA) circuit includes a first input resistor coupled between a first input node and a first summing node and a second input resistor coupled between a second input node and a second summing node. The PGA circuit further includes a first variable reference resistor coupled between a third input node and the first summing node, a second variable reference resistor coupled between a fourth input node and the second summing node, and an operational amplifier having first and second inputs coupled to respective ones of the first and second summing nodes and first and second outputs coupled to respective ones of the first and second output nodes. At least of the first and second reference resistors may include an R-2R ladder circuit.

Abstract translation: 可编程增益放大器（PGA）电路包括耦合在第一输入节点和第一求和节点之间的第一输入电阻器以及耦合在第二输入节点和第二求和节点之间的第二输入电阻器。 PGA电路还包括耦合在第三输入节点和第一求和节点之间的第一可变参考电阻器，耦合在第四输入节点和第二求和节点之间的第二可变参考电阻器，以及运算放大器，其具有耦合到 第一和第二求和节点中的相应的，以及耦合到第一和第二输出节点中的相应的第一和第二输出节点的第一和第二输出。 至少第一和第二参考电阻器可以包括R-2R梯形电路。

公开(公告)号：US09917240B2

公开(公告)日：2018-03-13

申请号：US14740466

申请日：2015-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwang-Ho Kim ,  Jun-Hyeok Yang ,  Hyung-Jong Ko ,  Se-Ki Kim ,  Ho-Jin Park ,  Se-Ra An

IPC: H01L35/00 ,  H01L37/00 ,  H01L29/76 ,  H01L21/70 ,  H01L35/32 ,  H01L25/18 ,  H01L27/16

CPC classification number: H01L35/32 ,  H01L25/18 ,  H01L27/16 ,  H01L2924/0002 ,  Y10S257/93

Abstract: A thermoelectric element is provided as follows. First and second semiconductor fin structures are disposed on a semiconductor substrate. Each semiconductor fin structure extends in a first direction, protruding from the semiconductor substrate. First and second semiconductor nanowires are disposed on the first and second semiconductor fin structures, respectively. The first semiconductor nanowires include first impurities. The second semiconductor nanowires include second impurities different from the first impurities. A first electrode is connected to first ends of the first and second semiconductor nanowires. A second electrode is connected to second ends of the first semiconductor nanowires. A third electrode is connected to second ends of the second semiconductor nanowires.