公开(公告)号：US10672790B2

公开(公告)日：2020-06-02

申请号：US16180609

申请日：2018-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Han Geun Yu ,  Daehyun Jang

IPC: H01L21/311 ,  H01L21/033 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/10 ,  H01L21/02

Abstract: Methods of fabricating a three-dimensional semiconductor memory device are provided. A method may include forming a mold structure on a substrate including channel regions and a non-channel region between the channel regions, and forming, on the mold structure, a multilayered mask layer including a first mask layer, an etch stop layer, and a second mask layer that are sequentially stacked. The multilayered mask layer may include mask holes exposing the mold structure in the channel regions, dummy mask holes exposing the first mask layer in the non-channel region, and buffer spacers covering sidewalls of the second mask layer exposed by the mask holes and the dummy mask holes. The method may include etching the mold structure using the multilayered mask layer as an etch mask to form channel holes in the channel regions.

公开(公告)号：US11521983B2

公开(公告)日：2022-12-06

申请号：US16863381

申请日：2020-04-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Han Geun Yu ,  Daehyun Jang

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11568 ,  H01L21/033 ,  H01L21/311 ,  H01L29/10 ,  H01L21/02

Abstract: Methods of fabricating a three-dimensional semiconductor memory device are provided. A method may include forming a mold structure on a substrate including channel regions and a non-channel region between the channel regions, and forming, on the mold structure, a multilayered mask layer including a first mask layer, an etch stop layer, and a second mask layer that are sequentially stacked. The multilayered mask layer may include mask holes exposing the mold structure in the channel regions, dummy mask holes exposing the first mask layer in the non-channel region, and buffer spacers covering sidewalls of the second mask layer exposed by the mask holes and the dummy mask holes. The method may include etching the mold structure using the multilayered mask layer as an etch mask to form channel holes in the channel regions.

公开(公告)号：US08652968B2

公开(公告)日：2014-02-18

申请号：US13719235

申请日：2012-12-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Han Geun Yu ,  Eunsung Kim ,  Chulho Shin

IPC: H01L21/311

CPC classification number: H01L21/02337 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76816 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675

Abstract: A method of fabricating a semiconductor device may include forming spacer line patterns on sidewalls of photoresist. A planarization etching process may be performed on a subsequently added planarization layer, after forming a mesh-shaped mask pattern from the spacer line patterns.

Abstract translation: 制造半导体器件的方法可以包括在光致抗蚀剂的侧壁上形成间隔线图案。 在从隔离线图案形成网状掩模图案之后，可以对随后添加的平坦化层执行平面化蚀刻工艺。

公开(公告)号：US20190288001A1

公开(公告)日：2019-09-19

申请号：US16180609

申请日：2018-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Han Geun Yu ,  Daehyun Jang

IPC: H01L27/11582 ,  H01L21/033 ,  H01L21/311 ,  H01L27/11568 ,  H01L27/11565

Abstract: Methods of fabricating a three-dimensional semiconductor memory device are provided. A method may include forming a mold structure on a substrate including channel regions and a non-channel region between the channel regions, and forming, on the mold structure, a multilayered mask layer including a first mask layer, an etch stop layer, and a second mask layer that are sequentially stacked. The multilayered mask layer may include mask holes exposing the mold structure in the channel regions, dummy mask holes exposing the first mask layer in the non-channel region, and buffer spacers covering sidewalls of the second mask layer exposed by the mask holes and the dummy mask holes. The method may include etching the mold structure using the multilayered mask layer as an etch mask to form channel holes in the channel regions.