公开(公告)号：US20250115785A1

公开(公告)日：2025-04-10

申请号：US18771727

申请日：2024-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonki HUR ,  Seokjoo KIM ,  Daehoon YANG ,  Sanghyun PARK ,  Gayoung KIM ,  Sangkyun KIM ,  Inkwon KIM ,  Eunho SONG ,  Jaekwang CHOI

IPC: C09G1/02 ,  B24B37/04 ,  C09K3/14 ,  C09K15/30 ,  H01L21/321

Abstract: A slurry composition for chemical mechanical metal polishing includes a corrosion inhibitor, abrasive particles, an oxidizing agent, and a solvent. The corrosion inhibitor includes a C2 to C30 aliphatic heterocyclic compound including at least one nitrogen atom in the ring and at least one functional group selected from a halogen, an amine group, a cyclic amine group, a nitro group, an amide group, a carboxyl group, a hydroxy group, a thiol group, an alkoxy group, a C10 to C30 alkyl group, or an ester group; or a C2 to C30 aromatic heterocyclic compound including at least one nitrogen atom in the ring and at least one functional group selected from a halogen, an amine group, a cyclic amine group, a nitro group, an amide group, a carboxyl group, a hydroxy group, a thiol group, an alkoxy group, a C10 to C30 alkyl group, and an ester group; or a combination thereof.

公开(公告)号：US20240243090A1

公开(公告)日：2024-07-18

申请号：US18618133

申请日：2024-03-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaekul LEE ,  Hyungsun JANG ,  Gayoung KIM ,  Minjeong SHIN

IPC: H01L23/00 ,  H01L25/10

CPC classification number: H01L24/20 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/2101 ,  H01L2224/2105 ,  H01L2224/221 ,  H01L2224/73101 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058

Abstract: A semiconductor package includes a lower redistribution layer disposed on a lower surface of the semiconductor chip including an insulating layer, a redistribution pattern, a via, an under bump metal (UBM), and a post disposed on the redistribution pattern. The post vertically overlaps with the UBM. A mold layer is on the lower redistribution layer and surrounds the semiconductor chip. A connecting terminal is connected to the UBM. The UBM includes a first section contacting the redistribution pattern, and a second section contacting the insulating layer. The post has a ring shape having an inner surface and an outer surface when viewed in a top view. A maximum width of the inner surface is less than a maximum width of an upper surface of the first section. A maximum width of the outer surface is greater than the maximum width of the upper surface of the first section.

公开(公告)号：US20220246568A1

公开(公告)日：2022-08-04

申请号：US17479042

申请日：2021-09-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaekul LEE ,  Hyungsun JANG ,  Gayoung KIM ,  Minjeong SHIN

IPC: H01L23/00 ,  H01L25/10

Abstract: A semiconductor package includes a lower redistribution layer disposed on a lower surface of the semiconductor chip including an insulating laver, a redistribution pattern, a via, an under bump metal (UBM), and a post disposed on the redistribution pattern. The post vertically overlaps with the UBM. A mold layer is on the lower redistribution layer and surrounds the semiconductor chip. A connecting terminal is connected to the UBM. The UBM includes a first section contacting the redistribution pattern, and a second section contacting the insulating layer. The lost has a ring shape having an inner surface and an outer surface when viewed a top view. A maximum width of the inner surface is less than a Maximum width of an upper surface of the first section. A maximum width of the outer surface is greater than the maximum width of the upper surface of the first section.