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公开(公告)号：US12111674B2
公开(公告)日：2024-10-08
申请号：US17720483
申请日：2022-04-14
发明人： Choonghoon Park , Jong-Lae Park , Bumgyu Park , Youngtae Lee , Donghee Han
IPC分类号： G06F1/26 , G05F1/46 , G05F1/66 , G06F1/32 , G06F1/3234 , G06F1/3296 , G06F15/78
CPC分类号： G05F1/66 , G05F1/462 , G06F1/3243 , G06F1/3296 , G06F15/7807
摘要： An operating method of a system-on-chip (SoC) which includes a processor including a first core and a dynamic voltage and frequency scaling (DVFS) module and a clock management unit (CMU) for supplying an operating clock to the first core, the operating method including: obtaining a required performance of the first core; finding available frequencies meeting the required performance; obtaining information for calculating energy consumption for each of the available frequencies; calculating the energy consumption for each of the available frequencies, based on the information; determining a frequency, which causes minimum energy consumption, from among the available frequencies as an optimal frequency; and
adjusting an operating frequency to be supplied to the first core to the optimal frequency.-
公开(公告)号：US20210081027A1
公开(公告)日：2021-03-18
申请号：US16861383
申请日：2020-04-29
发明人： Jonglae Park , Youngtae Lee , Choonghoon Park , Hyunchul Seok , Kwanjin Jung
IPC分类号： G06F1/3296 , G06F1/324
摘要： Dynamic voltage and frequency scaling (DVFS) is performed based on a power step by setting a plurality of power levels corresponding to a plurality of available frequencies of a clock signal for an operation of a processor, setting a plurality of power steps corresponding to the plurality of available frequencies, and controlling a conversion between the plurality of power levels based on a utilization of the processor and the plurality of power steps. Performance and power consumption of a processor are controlled efficiently by performing power level conversion based on the power step.
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公开(公告)号：US11243604B2
公开(公告)日：2022-02-08
申请号：US16861383
申请日：2020-04-29
发明人： Jonglae Park , Youngtae Lee , Choonghoon Park , Hyunchul Seok , Kwanjin Jung
IPC分类号： G06F1/00 , G06F1/3296 , G06F1/324
摘要： Dynamic voltage and frequency scaling (DVFS) is performed based on a power step by setting a plurality of power levels corresponding to a plurality of available frequencies of a clock signal for an operation of a processor, setting a plurality of power steps corresponding to the plurality of available frequencies, and controlling a conversion between the plurality of power levels based on a utilization of the processor and the plurality of power steps. Performance and power consumption of a processor are controlled efficiently by performing power level conversion based on the power step.
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4.发明授权公开(公告)号：US11921554B2
公开(公告)日：2024-03-05
申请号：US17718699
申请日：2022-04-12
发明人： Jong-Lae Park , Bumgyu Park , Hanjun Shin , Daeyeong Lee , Choonghoon Park , Dahye Choi , Donghee Han
IPC分类号： G06F1/20 , G06F1/03 , G06F1/324 , G06F1/3296
CPC分类号： G06F1/206 , G06F1/03 , G06F1/324 , G06F1/3296
摘要： Disclosed is an apparatus for dynamic thermal management, which includes a thermal management unit that determines whether there is a need to perform thermal management on a processor based on temperatures measured from a plurality of temperature sensors included in the processor and generates an indication signal, and a controller that performs the thermal management on the processor in response to the indication signal, by using a first method of adjusting a state of each of a plurality of cores included in the processor, a second method of adjusting a level of an operating voltage and a frequency of a clock signal, which are provided to the processor, and/or a third method for adjusting only the frequency of the clock signal to be provided to the processor, and where each of the plurality of cores is in a wake-up state or an idle state.
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5.发明授权公开(公告)号：US11768702B2
公开(公告)日：2023-09-26
申请号：US17112008
申请日：2020-12-04
发明人： Hyunchul Seok , Choonghoon Park , Byungsoo Kwon , Bumgyu Park , Jonglae Park , Junhwa Seo , Youngcheol Shin , Youngtae Lee
CPC分类号： G06F9/4881 , G06F9/3836 , G06F9/3877 , G06F9/50 , G06F9/505 , G06F9/5005 , G06F9/5027 , G06F9/5033 , G06F9/541 , G06F9/4893
摘要： An apparatus and a method for scheduling a task in an electronic device including a heterogeneous multi-processor are provided. The electronic device includes a memory and a processor operatively connected to the memory and including a plurality of heterogeneous cores. The processor may be configured to identify, when a task to be scheduled occurs, a scheduling group having the task among a plurality of predefined scheduling groups, and to perform scheduling for the task, based on the identified scheduling group having the task and a priority of the task.
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