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公开(公告)号：US11301780B2
公开(公告)日：2022-04-12
申请号：US16791111
申请日：2020-02-14
发明人： Sripurna Mutalik , Nidhal Kottamoola Ibrahimkutty , Naresh Kumar Narasimma Moorthy , Manith Shetty , Anuradha Kanukotla , Jaeho Kim , Kwanjin Jung , Wonseo Choi
IPC分类号： G06N20/00 , G06F3/0482 , G06F16/908 , G06F11/34
摘要： A method for machine learning based prediction of at least one subsequent UI layout is provided. The method may include detecting, by the electronic device, a first transition event. Further, the method may include identifying, by the electronic device, a UI layout associated with a first application of the electronic device. Further, the method may include predicting, by the electronic device, the at least one subsequent UI layout to be displayed based on at least one transition parameter, wherein the at least one subsequent UI layout is associated with at least one of the first application or at least one second application. Further, the method may include loading, by the electronic device, the at least one subsequent UI layout in a memory of the electronic device.
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公开(公告)号：US20210081027A1
公开(公告)日：2021-03-18
申请号：US16861383
申请日：2020-04-29
发明人： Jonglae Park , Youngtae Lee , Choonghoon Park , Hyunchul Seok , Kwanjin Jung
IPC分类号： G06F1/3296 , G06F1/324
摘要： Dynamic voltage and frequency scaling (DVFS) is performed based on a power step by setting a plurality of power levels corresponding to a plurality of available frequencies of a clock signal for an operation of a processor, setting a plurality of power steps corresponding to the plurality of available frequencies, and controlling a conversion between the plurality of power levels based on a utilization of the processor and the plurality of power steps. Performance and power consumption of a processor are controlled efficiently by performing power level conversion based on the power step.
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公开(公告)号：US11243604B2
公开(公告)日：2022-02-08
申请号：US16861383
申请日：2020-04-29
发明人： Jonglae Park , Youngtae Lee , Choonghoon Park , Hyunchul Seok , Kwanjin Jung
IPC分类号： G06F1/00 , G06F1/3296 , G06F1/324
摘要： Dynamic voltage and frequency scaling (DVFS) is performed based on a power step by setting a plurality of power levels corresponding to a plurality of available frequencies of a clock signal for an operation of a processor, setting a plurality of power steps corresponding to the plurality of available frequencies, and controlling a conversion between the plurality of power levels based on a utilization of the processor and the plurality of power steps. Performance and power consumption of a processor are controlled efficiently by performing power level conversion based on the power step.
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