公开(公告)号：US10559336B2

公开(公告)日：2020-02-11

申请号：US16140066

申请日：2018-09-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeon-Wu Kim ,  Seok-Won Ahn ,  Chan-Ho Yoon

IPC: G11C7/00 ,  G11C7/22 ,  G06F12/02 ,  H03L7/081 ,  G06F5/08 ,  G06F13/16 ,  G06F1/08 ,  G06F1/12

Abstract: A memory controller is used to control a first storage block having a first data rate and a second storage block having a second data rate. The memory controller includes; a memory interface that transceives a data signal and a data strobe signal with the first and second storage blocks, and a sub controller that stores access information about the first data rate and the second data rate. The sub controller may include a delay lookup table storing access information including first strobe adjustment timing information defining a first data strobe signal provided to the first storage block, and second strobe adjustment timing information defining a second data strobe signal provided to the second storage block.

公开(公告)号：US10691338B2

公开(公告)日：2020-06-23

申请号：US15147924

申请日：2016-05-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Sub Song ,  Chan-Ho Yoon ,  Nam-Wook Kang ,  Jung-Pil Lee ,  Tae-Young Lee

IPC: G06F3/06

Abstract: A data storage device includes a controller connected via a plurality of channels to a plurality of clusters, wherein each cluster comprises a scale-out device including a scale-out controller and a buffer. The scale-out controller is connected to a plurality of sub-channels, each one of the plurality of sub-channels connecting a group of non-volatile memory (NVM) devices, such that the scale-out controller controls execution of data processing operations directed to any one of the NVM devices and the buffer.