公开(公告)号：US20250048655A1

公开(公告)日：2025-02-06

申请号：US18737537

申请日：2024-06-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bonjae KOO ,  Seulji Song ,  Youngsun Song

IPC: H10B99/00

Abstract: Provided is a semiconductor memory device including: cell blocks, each including a folding structure in which electrode structures and insulating structures are alternately provided, wherein the electrode structures and the insulating structures extend in a vertical direction and are connected with each other so as to have at least two U-shaped structures forming villus shapes in a plan view, the electrode structures include a vertical electrode and a switching material layer, and the cell blocks are provided in a first horizontal direction and a second horizontal direction intersecting the first horizontal direction; and a gate stack structure including gate electrodes and interlayer insulating layers that are alternately stacked in the vertical direction along sidewalls of the electrode structures.

公开(公告)号：US20250063957A1

公开(公告)日：2025-02-20

申请号：US18657229

申请日：2024-05-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bonjae KOO ,  Seulji SONG ,  Youngsun SONG

IPC: H10N70/00 ,  H10B63/00 ,  H10B63/10

Abstract: According to an aspect of the disclosure, a vertical memory device may include: a substrate; a plurality of electrode structures extending in a vertical direction on the substrate; a word line cut disposed apart from the plurality of electrode structures in a horizontal direction and extending in the vertical direction; and a gate stack structure may include gate electrodes and interlayer insulating layers alternately stacked on the substrate along a sidewall of each of the plurality of electrode structures and the word line cut, wherein the gate electrodes may be electrically connected to the plurality of electrode structures. In a plan view, the word line cut may be wavy-shaped.

公开(公告)号：US20250040145A1

公开(公告)日：2025-01-30

申请号：US18786011

申请日：2024-07-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bonjae KOO ,  Seulji Song ,  Youngsun Song

IPC: H10B51/20 ,  H01L29/78 ,  H10B51/10 ,  H10B51/40

Abstract: A semiconductor memory device is provided. The semiconductor device includes: a stacked structure with word line plates and mold insulating layers which extend in first and second horizontal directions, and are alternately stacked in a vertical direction in a cell array region and an extension region, the plurality of word line plates forming a staircase structure in the extension region; a vertical bit line extending into the stacked structure in the cell array region; a plurality of selection layers between the plurality of word line plates and the vertical bit line; and a vertical channel transistor connected to one end of the vertical bit line. A first thickness of each of the plurality of mold insulating layers is about 1.5 times to about 3 times a second thickness of each of the plurality of word line plates.