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公开(公告)号:US20220232186A1
公开(公告)日:2022-07-21
申请号:US17523100
申请日:2021-11-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Hyuk OH , Sungyong KIM , Beomsu YUN
Abstract: An image sensor is provided. The image sensor includes a counting code generator configured to generate a counting code, a pixel array including at least one pixel, a correlated double sampling (CDS) circuit configured to compare a magnitude of a pixel signal output from the at least one pixel with a magnitude of a ramp signal and to output a corresponding comparison signal, a pulse generator configured to generate a pulse signal synchronized with a first clock signal based on the comparison signal, and a counter circuit configured to latch a value of the counting code to correspond to a transition of a level of the comparison signal based on the pulse signal.
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公开(公告)号:US20240214552A1
公开(公告)日:2024-06-27
申请号:US18391062
申请日:2023-12-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Beomsu YUN , Hyuk OH
CPC classification number: H04N17/002 , H04N25/7795 , H04N25/78
Abstract: Provided is an image sensor including a pixel array that includes a plurality of pixels, wherein each of the plurality of pixels is configured to generate an analog signal in response to incident light; an analog-to-digital converter that includes a counter, wherein the analog-to-digital converter is configured to convert the analog signal into a digital signal; and a test circuit that is configured to change a reset code according to a horizontal time period, wherein the reset code corresponds to a first counting value during a reset time period of a test mode according to a count clock signal, and wherein the test circuit is configured to test a counting operation of the counter based on the reset code that changes according to the horizontal time period.
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公开(公告)号:US20230155602A1
公开(公告)日:2023-05-18
申请号:US17985642
申请日:2022-11-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jaehoon JUN , Beomsu YUN
CPC classification number: H03M1/183 , H03M1/1295 , H03F1/0222
Abstract: In some embodiments, a circuit includes a first amplifier, a second amplifier, and a counter. The first amplifier operates based on a first power supply voltage and generates a first output signal by comparing a ramp signal and a reset signal of a pixel signal output from a pixel array during a first operation period and comparing the ramp signal and an image signal of the pixel signal output from the pixel array during a second operation period. The second amplifier operates based on the first power supply voltage, generates a second output signal based on the first output signal and adjust a voltage level of the second output signal from a low level to a third level. The counter operates based on a second power supply voltage, counts pulses of the second output signal, and outputs a counting result as a digital signal.
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