Abstract:
Disclosed herein is a multi-layer type coreless substrate, including: a first insulating layer including at least one first pillar; a plurality of insulating layers laminated on one surface or both surfaces of the first insulating layer, each including at least one circuit layer and at least another pillar connected to the circuit layer; and a plurality of outermost circuit layers contacting a pillar disposed on an outermost insulating layer of the plurality of insulating layers.
Abstract:
A semiconductor device includes: a chip having an active surface having connection pads disposed thereon; an encapsulant encapsulating at least portions of the chip; a connection member disposed on the active surface of the chip and including a redistribution layer electrically connected to the connection pads; a passivation layer disposed on the connection member; and an under bump metallurgy (UBM) layer at least partially embedded in the passivation layer and electrically connected to the redistribution layer of the connection member. The UBM layer includes a UBM pad partially embedded in the passivation layer and a UVM via penetrating through a portion of the passivation layer and electrically connecting the redistribution layer of the connection member and the UBM pad to each other. A portion of a side surface of the UBM pad is exposed through an opening formed in the passivation layer and the opening surrounds the UBM pad.
Abstract:
A semiconductor device includes: a chip having an active surface having connection pads disposed thereon; an encapsulant encapsulating at least portions of the chip; a connection member disposed on the active surface of the chip and including a redistribution layer electrically connected to the connection pads; a passivation layer disposed on the connection member; and an under bump metallurgy (UBM) layer at least partially embedded in the passivation layer and electrically connected to the redistribution layer of the connection member. The UBM layer includes a UBM pad partially embedded in the passivation layer and a UVM via penetrating through a portion of the passivation layer and electrically connecting the redistribution layer of the connection member and the UBM pad to each other. A portion of a side surface of the UBM pad is exposed through an opening formed in the passivation layer and the opening surrounds the UBM pad.