公开(公告)号：US20080029843A1

公开(公告)日：2008-02-07

申请号：US11873197

申请日：2007-10-16

Applicant: Roger Booth ,  William Hovis ,  Jack Mandelman ,  William Tonti

Inventor： Roger Booth ,  William Hovis ,  Jack Mandelman ,  William Tonti

IPC: H01L29/41

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An E-fuse and a method for fabricating an E-fuse integrating polysilicon resistor masks, and a design structure on which the subject E-fuse circuit resides are provided. The E-fuse includes a polysilicon layer defining a fuse shape including a cathode, an anode, and a fuse neck connected between the cathode and the anode silicide formation. A silicide formation is formed on the polysilicon layer with an unsilicided portion extending over a portion of the cathode adjacent the fuse neck. The unsilicided portion substantially prevents current flow in the silicide formation region of the cathode, with electromigration occurring in the fuse neck during fuse programming. The unsilicided portion has a substantially lower series resistance than the series resistance of the fuse neck.

Abstract translation: 一种电熔丝和一种用于制造集成多晶硅电阻掩模的电子熔丝的方法，以及设置有被检体E熔丝回路的设计结构。 电熔丝包括限定熔丝形状的多晶硅层，其包括阴极，阳极和连接在阴极和阳极硅化物层之间的保险丝颈。 硅化物形成在多晶硅层上形成，其中非硅化部分在靠近熔丝颈部的阴极的一部分上延伸。 非接触部分基本上防止电流在阴极的硅化物形成区域中流动，在保险丝编程期间在保险丝颈部发生电迁移。 非接触部分具有比熔丝颈部的串联电阻显着更低的串联电阻。

公开(公告)号：US20080042219A1

公开(公告)日：2008-02-21

申请号：US11923121

申请日：2007-10-24

Applicant: Roger Booth ,  William Hovis ,  Jack Mandelman

Inventor： Roger Booth ,  William Hovis ,  Jack Mandelman

IPC: H01L29/94

CPC classification number: H01L29/7851 ,  H01L29/66795

Abstract: A finFET, a method of fabricating the finFET and a design structure of the finFET. The method includes: forming a silicon fin on a top surface of a silicon substrate; forming a gate dielectric on opposite sidewalls of the fin; forming a gate electrode over a channel region of the fin, the gate electrode in direct physical contact with the gate dielectric layer on the opposite sidewalls of the fin; forming a first source/drain in the fin on a first side of the channel region and forming a second source/drain in the fin on a second side of the channel region; removing a portion of the substrate from under at least a portion of the first and second source/drains to create a void; and filling the void with a dielectric material. The finFET includes a body contact between the silicon body of the finFET and the substrate.

Abstract translation: finFET，finFET的制造方法以及finFET的设计结构。 该方法包括：在硅衬底的顶表面上形成硅翅片; 在翅片的相对侧壁上形成栅电介质; 在鳍片的沟道区域上形成栅电极，栅电极与翅片的相对侧壁上的栅介电层直接物理接触; 在所述通道区域的第一侧上在所述翅片中形成第一源极/漏极，并且在所述沟道区域的第二侧上在所述鳍片中形成第二源极/漏极; 从第一和第二源/排水沟的至少一部分下方去除衬底的一部分以产生空隙; 并用介电材料填充空隙。 finFET包括在finFET的硅体和衬底之间的体接触。

公开(公告)号：US20070262413A1

公开(公告)日：2007-11-15

申请号：US11382808

申请日：2006-05-11

Applicant: Roger Booth ,  William Hovis ,  Jack Mandelman ,  William Tonti

Inventor： Roger Booth ,  William Hovis ,  Jack Mandelman ,  William Tonti

IPC: H01L29/00

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An E-fuse and a method for fabricating an E-fuse are provided integrating polysilicon resistor masks. The E-fuse includes a polysilicon layer defining a fuse shape including a cathode, an anode, and a fuse neck connected between the cathode and the anode silicide formation. A silicide formation is formed on the polysilicon layer with an unsilicided portion extending over a portion of the cathode adjacent the fuse neck. The unsilicided portion substantially prevents current flow in the silicide formation region of the cathode, with electromigration occurring in the fuse neck during fuse programming. The unsilicided portion has a substantially lower series resistance than the series resistance of the fuse neck.

Abstract translation: 集成了多晶硅电阻掩模的电子熔丝和用于制造电熔丝的方法被提供。 电熔丝包括限定熔丝形状的多晶硅层，其包括阴极，阳极和连接在阴极和阳极硅化物层之间的保险丝颈。 硅化物形成在多晶硅层上形成，其中非硅化部分在靠近熔丝颈部的阴极的一部分上延伸。 非接触部分基本上防止电流在阴极的硅化物形成区域中流动，在保险丝编程期间在保险丝颈部发生电迁移。 非接触部分具有比熔丝颈部的串联电阻显着更低的串联电阻。

公开(公告)号：US20070210411A1

公开(公告)日：2007-09-13

申请号：US11372334

申请日：2006-03-09

Applicant: William Hovis ,  Louis Hsu ,  Jack Mandelman ,  William Tonti ,  Chih-Chao Yang

Inventor： William Hovis ,  Louis Hsu ,  Jack Mandelman ,  William Tonti ,  Chih-Chao Yang

IPC: H01L21/82 ,  H01L29/00

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Electrically programmable fuse structures for an integrated circuit and methods of fabrication thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first terminal portion and the second terminal portion reside at different heights relative to a supporting surface of the fuse structure, and the interconnecting fuse element transitions between the different heights of the first terminal portion and the second terminal portion. The first and second terminal portions are oriented parallel to the supporting surface, while the fuse element includes a portion oriented orthogonal to the supporting surface, and includes at least one right angle bend where transitioning from at least one of the first and second terminal portions to the orthogonal oriented portion of the fuse element.

Abstract translation: 提出了用于集成电路的电可编程熔丝结构及其制造方法，其中电可编程熔丝具有由熔丝元件互连的第一端子部分和第二端子部分。 第一端子部分和第二端子部分相对于熔丝结构的支撑表面驻留在不同的高度处，并且互连熔丝元件在第一端子部分和第二端子部分的不同高度之间转变。 第一端子部分和第二端子部分平行于支撑表面定向，而熔丝元件包括垂直于支撑表面定向的部分，并且包括至少一个直角弯曲部，其从第一和第二端子部分中的至少一个过渡到 保险丝元件的正交取向部分。

公开(公告)号：US20070010059A1

公开(公告)日：2007-01-11

申请号：US11522164

申请日：2006-09-15

Applicant: William Hovis ,  Jack Mandelman

Inventor： William Hovis ,  Jack Mandelman

IPC: H01L21/336

CPC classification number: H01L29/4908 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/785

Abstract: In a first aspect, a first method is provided for semiconductor device manufacturing. The first method includes the steps of (1) forming a first side of a fin of a fin field effect transistor (FinFET); (2) processing the first side of the fin; and (3) forming a second side of the fin while supporting the first side of the fin. Numerous other aspects are provided.

Abstract translation: 在第一方面中，提供了半导体器件制造的第一种方法。 第一种方法包括以下步骤：（1）形成鳍状场效应晶体管（FinFET）的鳍的第一侧; （2）处理鳍片的第一面; 和（3）在支撑翅片的第一侧的同时形成翅片的第二侧。 提供了许多其他方面。

公开(公告)号：US20060261414A1

公开(公告)日：2006-11-23

申请号：US11132652

申请日：2005-05-19

Applicant: William Hovis ,  Jack Mandelman

Inventor： William Hovis ,  Jack Mandelman

IPC: H01L29/76

CPC classification number: H01L29/4908 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/785

Abstract: In a first aspect, a first method is provided for semiconductor device manufacturing. The first method includes the steps of (1) forming a first side of a fin of a fin field effect transistor (FinFET); (2) processing the first side of the fin; and (3) forming a second side of the fin while supporting the first side of the fin. Numerous other aspects are provided.

Abstract translation: 在第一方面中，提供了半导体器件制造的第一种方法。 第一种方法包括以下步骤：（1）形成鳍状场效应晶体管（FinFET）的鳍的第一侧; （2）处理鳍片的第一面; 和（3）在支撑翅片的第一侧的同时形成翅片的第二侧。 提供了许多其他方面。

公开(公告)号：US20080102627A1

公开(公告)日：2008-05-01

申请号：US11876230

申请日：2007-10-22

Applicant: Todd Christensen ,  Richard Donze ,  William Hovis ,  Terrance Kueper ,  John Sheets

Inventor： Todd Christensen ,  Richard Donze ,  William Hovis ,  Terrance Kueper ,  John Sheets

IPC: H01L21/44

CPC classification number: H01L21/28518 ,  H01L21/76889 ,  H01L21/76895 ,  H01L29/458 ,  H01L29/785

Abstract: An apparatus and method are disclosed for an improved semiconductor interconnect scheme using a simplified process. In an embodiment of the apparatus, a polysilicon shape is formed on a silicon area. The polysilicon shape is created having a bridging vertex. When a spacer is created on the polysilicon shape, the spacer width is formed to be small enough near the bridging vertex to allow a silicide bridge to form that creates an electrical coupling between the silicon area and the bridging vertex. Semiconductor devices and circuits are created using the improved semiconductor interconnect scheme using the simplified process.

公开(公告)号：US20060109726A1

公开(公告)日：2006-05-25

申请号：US10994087

申请日：2004-11-19

Applicant: William Cochran ,  William Hovis

Inventor： William Cochran ,  William Hovis

IPC: G11C29/00

CPC classification number: G11C29/14 ,  G11C11/401 ,  G11C29/18

Abstract: A method, apparatus, and computer program product are provided for implementing an enhanced DRAM interface checking. An interface check mode enables interface checking using a refresh command for a DRAM. A predefined address pattern is provided for the interface address inputs during a refresh command cycle. Interface address inputs are checked for a proper value being applied and an error is signaled for unexpected results. An extended test mode includes further testing during a cycle after the refresh command cycle. Then command inputs also are checked for a proper value being applied and an error is signaled for unexpected results.

Abstract translation: 提供了一种用于实现增强的DRAM接口检查的方法，装置和计算机程序产品。 接口检查模式使用DRAM的刷新命令进行接口检查。 在刷新命令循环期间为接口地址输入提供预定义的地址模式。 检查接口地址输入是否正在应用值，并发出错误信号，以获取意外结果。 扩展测试模式包括在刷新命令周期之后的一个周期内的进一步测试。 然后，还将检查命令输入是否正在应用值，并发出错误信号，以获得意外结果。

公开(公告)号：US20060090112A1

公开(公告)日：2006-04-27

申请号：US10961745

申请日：2004-10-08

Applicant: William Cochran ,  William Hovis ,  Paul Rudrud

Inventor： William Cochran ,  William Hovis ,  Paul Rudrud

IPC: G01R31/28 ,  G06F11/00

CPC classification number: G06F12/0804 ,  G06F12/084

Abstract: Verification operations are utilized to effectively verify multiple associated write operations. A verification operation may be initiated after the issuance of a plurality of write operations that initiate the storage of data to a memory storage device, and may be configured to verify only a subset of the data written to the memory storage device by the plurality of write operations. As a result, verification operations are not required to be performed after each write operation, and consequently, the number of verification operations, and thus the processing and communication bandwidth consumed thereby, can be substantially reduced.

公开(公告)号：US20080093683A1

公开(公告)日：2008-04-24

申请号：US11876379

申请日：2007-10-22

Applicant: Todd Christensen ,  Richard Donze ,  William Hovis ,  Terrance Kueper ,  John Sheets

Inventor： Todd Christensen ,  Richard Donze ,  William Hovis ,  Terrance Kueper ,  John Sheets

IPC: H01L29/78

CPC classification number: H01L21/28518 ,  H01L21/76889 ,  H01L21/76895 ,  H01L29/458 ,  H01L29/785

Abstract: An apparatus and method are disclosed for an improved semiconductor interconnect scheme using a simplified process. In an embodiment of the apparatus, a polysilicon shape is formed on a silicon area. The polysilicon shape is created having a bridging vertex. When a spacer is created on the polysilicon shape, the spacer width is formed to be small enough near the bridging vertex to allow a silicide bridge to form that creates an electrical coupling between the silicon area and the bridging vertex. Semiconductor devices and circuits are created using the improved semiconductor interconnect scheme using the simplified process.

Abstract translation: 公开了一种使用简化过程的改进的半导体互连方案的装置和方法。 在该装置的实施例中，在硅区域上形成多晶硅形状。 产生具有桥接顶点的多晶硅形状。 当在多晶硅形状上形成间隔物时，在桥接顶点附近形成足够小的间隔物宽度，以形成硅化物桥，从而在硅区域和桥接顶点之间产生电耦合。 使用简化的工艺使用改进的半导体互连方案创建半导体器件和电路。