公开(公告)号：US20160086870A1

公开(公告)日：2016-03-24

申请号：US14797092

申请日：2015-07-11

Applicant: Renesas Electronics Corporation

Inventor： Youichi ABE ,  Yuko SATO

IPC: H01L23/367 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/0655 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/4334 ,  H01L23/49827 ,  H01L24/09 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/04042 ,  H01L2224/301 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/1511 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A semiconductor device with improved heat radiation characteristics. It includes: a wiring board having a chip mounting surface and a plurality of electrode pads formed over the chip mounting surface; a semiconductor chip located over the chip mounting surface of the wiring board, having a plurality of bonding pads; a plurality of wires for coupling the electrode pads and the bonding pads; a heat slug located over the semiconductor chip; and a sealing member covering the chip mounting surface of the wiring board, the semiconductor chip, the wires, and the heat slug. A spacer lies between the chip mounting surface of the wiring board and the semiconductor chip and the sealing member lies between the semiconductor chip and the heat slug.

Abstract translation: 具有改善的热辐射特性的半导体器件。 它包括：具有芯片安装表面的布线板和形成在芯片安装表面上的多个电极焊盘; 位于布线板的芯片安装面上方的半导体芯片，具有多个焊盘; 用于耦合所述电极焊盘和所述焊盘的多根导线; 位于半导体芯片上方的散热片; 以及覆盖所述布线板的芯片安装面，所述半导体芯片，所述导线和所述热芯块的密封构件。 间隔件位于布线板的芯片安装表面和半导体芯片之间，并且密封构件位于半导体芯片和热芯块之间。

公开(公告)号：US20240304526A1

公开(公告)日：2024-09-12

申请号：US18437894

申请日：2024-02-09

Applicant: Renesas Electronics Corporation

Inventor： Masato NUMAZAKI ,  Youichi ABE ,  Tatsuaki TSUKUDA

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49513 ,  H01L23/3107 ,  H01L23/49541 ,  H01L24/06 ,  H01L24/48 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/06135 ,  H01L2224/32245 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265

Abstract: A semiconductor device includes: a die pad having an upper surface; a semiconductor chip; a plurality of leads; and a plurality of wires. The upper surface includes: a first region in which the semiconductor chip is mounted; a second region surrounding the first region in plan view; and a third region surrounding the second region in plan view. Also, a first metal film is provided in the second region. Further, a second metal film is provided in the third region. Here, in plan view, the semiconductor chip, the first meal film and the second metal film are spaced apart from one another. Also, the plurality of wires includes: a first wire bonded to each of a first electrode of the plurality of electrodes and the first metal film; and a second wire bonded to each of a first lead of the plurality of leads and the second metal film.