公开(公告)号：US20130071971A1

公开(公告)日：2013-03-21

申请号：US13677856

申请日：2012-11-15

Applicant: Renesas Electronics Corporation

Inventor： Ryoichi KAJIWARA ,  Shigehisa MOTOWAKI ,  Kazutoshi ITO ,  Toshiaki ISHII ,  Katsuo ARAI ,  Takuya NAKAJO ,  Hidemasa KAGII

IPC: H01L21/56

CPC classification number: H01L21/56 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/49524 ,  H01L23/49562 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/04026 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/29339 ,  H01L2224/29347 ,  H01L2224/32245 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/40249 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83439 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/8385 ,  H01L2224/83855 ,  H01L2224/83856 ,  H01L2224/8392 ,  H01L2224/83951 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/85447 ,  H01L2224/8592 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/05432 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01032 ,  H01L2924/3512 ,  H01L2224/48744

Abstract: In a structure of a semiconductor device, a Si chip and a metal leadframe are jointed by metallic bond via a porous joint layer made of high conductive metal, having a three-dimensional network structure and using Ag as a bonding material, and a film containing Zn oxide or Al oxide is formed on a surface of a semiconductor assembly contacting to a polymer resin. In this manner, by the joint with the joint layer having the porous structure mainly made of Ag, thermal stress load of the Si chip can be reduced, and fatigue life of the joint layer itself can be improved. Besides, since adhesion of the polymer resin to the film can be enhanced by the anchor effect, occurrence of cracks in a bonding portion can be prevented, so that a highly-reliable Pb-free semiconductor device can be provided.

Abstract translation: 在半导体器件的结构中，Si芯片和金属引线框通过金属接合，通过具有三维网状结构的高导电性金属的多孔接合层，使用Ag作为接合材料，以及含有 在与聚合物树脂接触的半导体组件的表面上形成氧化锌或氧化铝。 以这种方式，通过与主要由Ag形成的多孔结构的接合层的接合，可以降低Si片的热应力负荷，并且可以提高接合层本身的疲劳寿命。 此外，由于通过锚固效应可以提高聚合物树脂对膜的粘附性，可以防止接合部发生裂纹，从而可以提供高可靠性的无铅半导体器件。