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公开(公告)号：US11837524B2
公开(公告)日：2023-12-05
申请号：US17352612
申请日：2021-06-21
Applicant: Raytheon Company
Inventor： Paul T. Hartin , Kalin Spariosu , Thomas T. Leise , David A. Vasquez , Michael R. Patrizi
Abstract: A cooling device for integrated circuits. The device includes: a plurality TEC cooling cells arranged in an array, wherein each of the cells includes a controller coupled to at least one TEC device; and a single power connector that provides power to all the cells in the array. The controller of each cell in the array is operable to control the at least one TEC it is coupled to with power received from the single power connector.
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公开(公告)号：US20220406680A1
公开(公告)日：2022-12-22
申请号：US17352612
申请日：2021-06-21
Applicant: Raytheon Company
Inventor： Paul T. Hartin , Kalin Spariosu , Thomas T. Leise , David A. Vasquez , Michael R. Patrizi
Abstract: A cooling device for integrated circuits. The device includes: a plurality TEC cooling cells arranged in an array, wherein each of the cells includes a controller coupled to at least one TEC device; and a single power connector that provides power to all the cells in the array. The controller of each cell in the array is operable to control the at least one TEC it is coupled to with power received from the single power connector.
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公开(公告)号：US12301245B2
公开(公告)日：2025-05-13
申请号：US18114900
申请日：2023-02-27
Applicant: RAYTHEON COMPANY
Inventor： Paul T. Hartin , Kyle A. Steiner , Robert John Casey , Andres Lugo
IPC: H03M1/10
Abstract: A circuit and method for calibrating ADCs and DACs generates a calibration signal by a DAC; filters spurs from the calibration signal from the DAC to generate a filtered calibration signal; calculates ADC interleave calibration factors to improve performance metrics of the ADC, responsive to the filtered calibration signal; receives the calibration signal from the DAC and calculates DAC interleave calibration factors; generates a calibration signal with improved performance metrics, responsive to the DAC interleave calibration factors received from the ADC; and repeats the process until the performance of the ADC and DAC are within a predetermined range.
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Patent Agency Ranking
公开(公告)号：US20230089039A1
公开(公告)日：2023-03-23
申请号：US17948665
申请日：2022-09-20
Applicant: Raytheon Company
Inventor： Paul T. Hartin , Kalin Spariosu , Michael R. Patrizi
Abstract: A synthesizer including a controller configured to receive a first signal. A digital-to-analog converter (DAC) is coupled to the controller and is configured to generate a voltage bias based on the first signal. The voltage bias corresponds to a target resonant frequency. A semiconductor laser is coupled to the DAC and is configured to receive a second signal tone. The semiconductor laser generates a plurality of tone signals having octave multiples of a base sub-harmonic tone of the second signal tone.
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公开(公告)号：US12107945B2
公开(公告)日：2024-10-01
申请号：US18154117
申请日：2023-01-13
Applicant: Raytheon Company
Inventor： Paul T. Hartin , Ro S. Ko , Thomas T. Leise , Edward Escandon
IPC: H04L7/00
CPC classification number: H04L7/0008
Abstract: An electrical signal delay calibration system includes a device under test (DUT) and a digital signal processing chip including a plurality of signal lanes. Each signal lane includes a receive signal path in signal communication with a respective DUT receive path and a transmit signal path in signal communication with a respective DUT transmit path. A processor is configured to determine transmit pulse timestamps assigned to transmit signals transmitted on the transmit signal paths and to determine receive pulse timestamps assigned to receive signals received from the receive signal paths. The processor determines a lane asymmetry associated with each signal lane based on at least one of the transmit pulse timestamps and at least one of the receive pulse timestamps, and removes each of the lane asymmetries to minimize a signal delay in each signal lane among the plurality of signal lanes.
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公开(公告)号：US20240291498A1
公开(公告)日：2024-08-29
申请号：US18114900
申请日：2023-02-27
Applicant: RAYTHEON COMPANY
Inventor： Paul T. Hartin , Kyle A. Steiner , Robert John Casey , Andres Lugo
IPC: H03M1/10
CPC classification number: H03M1/1009
Abstract: A circuit and method for calibrating ADCs and DACs generates a calibration signal by a DAC; filters spurs from the calibration signal from the DAC to generate a filtered calibration signal; calculates ADC interleave calibration factors to improve performance metrics of the ADC, responsive to the filtered calibration signal; receives the calibration signal from the DAC and calculates DAC interleave calibration factors; generates a calibration signal with improved performance metrics, responsive to the DAC interleave calibration factors received from the ADC; and repeats the process until the performance of the ADC and DAC are within a predetermined range.
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公开(公告)号：US20240243897A1
公开(公告)日：2024-07-18
申请号：US18154117
申请日：2023-01-13
Applicant: Raytheon Company
Inventor： Paul T. Hartin , Ro S. Ko , Thomas T. Leise , Edward Escandon
IPC: H04L7/00
CPC classification number: H04L7/0008
Abstract: An electrical signal delay calibration system includes a device under test (DUT) and a digital signal processing chip including a plurality of signal lanes. Each signal lane includes a receive signal path in signal communication with a respective DUT receive path and a transmit signal path in signal communication with a respective DUT transmit path. A processor is configured to determine transmit pulse timestamps assigned to transmit signals transmitted on the transmit signal paths and to determine receive pulse timestamps assigned to receive signals received from the receive signal paths. The processor determines a lane asymmetry associated with each signal lane based on at least one of the transmit pulse timestamps and at least one of the receive pulse timestamps, and removes each of the lane asymmetries to minimize a signal delay in each signal lane among the plurality of signal lanes.
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公开(公告)号：US20220393429A1
公开(公告)日：2022-12-08
申请号：US17748698
申请日：2022-05-19
Applicant: Raytheon Company
Inventor： Kalin Spariosu , Paul T. Hartin , Michael R. Patrizi
Abstract: A synthesizer includes a first resonator mirror, a second resonator mirror, and a gain medium disposed within a laser resonator cavity defined by the first resonator mirror and the second resonator mirror. The synthesizer includes a saturable absorber operationally coupled to the gain medium and having active control such that the saturable absorber is configured to generate a waveform via an injection locking signal to create a mode locking effect, the waveform having a frequency comb defined by dimensions of the gain medium. The synthesizer also includes a crystal electro-optical modulator disposed within the laser resonator cavity. The waveform passes through the modulator to impinge on a photodiode to output an emission RF waveform. Changing the voltage applied to the modulator changes the index of refraction of the modulator, altering an optical path length of the laser resonator cavity to adjust a frequency of the emission RF waveform.
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