公开(公告)号：US11985259B2

公开(公告)日：2024-05-14

申请号：US17357067

申请日：2021-06-24

Applicant: RAYTHEON COMPANY

Inventor： Jennifer E. Howard ,  Colby K. Hoffman ,  Edward Escandon ,  Albert D. Marzullo ,  Ross MacKinnon ,  Maegen A. Forrer

IPC: H04L9/32 ,  H04L9/08

CPC classification number: H04L9/3278 ,  H04L9/0866 ,  H04L2209/12

Abstract: A multi-die device a first die containing a plurality of first die signal path elements configured to propagate a stimulus signal and a second die containing a plurality of second die signal path elements configured to propagate the stimulus signal. The multi-die device further includes an interposer configured to establish signal communication between the first die and the second die so as to deliver the stimulus signal from the plurality of first die signal path elements to the plurality of second die signal path elements to generate a propagation delay. The propagation delay is used to generate a single unified PUF response that is indicative of the authenticity of the multi-die device.

公开(公告)号：US12107945B2

公开(公告)日：2024-10-01

申请号：US18154117

申请日：2023-01-13

Applicant: Raytheon Company

Inventor： Paul T. Hartin ,  Ro S. Ko ,  Thomas T. Leise ,  Edward Escandon

IPC: H04L7/00

CPC classification number: H04L7/0008

Abstract: An electrical signal delay calibration system includes a device under test (DUT) and a digital signal processing chip including a plurality of signal lanes. Each signal lane includes a receive signal path in signal communication with a respective DUT receive path and a transmit signal path in signal communication with a respective DUT transmit path. A processor is configured to determine transmit pulse timestamps assigned to transmit signals transmitted on the transmit signal paths and to determine receive pulse timestamps assigned to receive signals received from the receive signal paths. The processor determines a lane asymmetry associated with each signal lane based on at least one of the transmit pulse timestamps and at least one of the receive pulse timestamps, and removes each of the lane asymmetries to minimize a signal delay in each signal lane among the plurality of signal lanes.

公开(公告)号：US20240243897A1

公开(公告)日：2024-07-18

申请号：US18154117

申请日：2023-01-13

Applicant: Raytheon Company

Inventor： Paul T. Hartin ,  Ro S. Ko ,  Thomas T. Leise ,  Edward Escandon

IPC: H04L7/00

CPC classification number: H04L7/0008

Abstract: An electrical signal delay calibration system includes a device under test (DUT) and a digital signal processing chip including a plurality of signal lanes. Each signal lane includes a receive signal path in signal communication with a respective DUT receive path and a transmit signal path in signal communication with a respective DUT transmit path. A processor is configured to determine transmit pulse timestamps assigned to transmit signals transmitted on the transmit signal paths and to determine receive pulse timestamps assigned to receive signals received from the receive signal paths. The processor determines a lane asymmetry associated with each signal lane based on at least one of the transmit pulse timestamps and at least one of the receive pulse timestamps, and removes each of the lane asymmetries to minimize a signal delay in each signal lane among the plurality of signal lanes.

公开(公告)号：US20220417041A1

公开(公告)日：2022-12-29

申请号：US17357067

申请日：2021-06-24

Applicant: RAYTHEON COMPANY

Inventor： Jennifer E. Howard ,  Colby K. Hoffman ,  Edward Escandon ,  Albert D. Marzullo ,  Ross MacKinnon ,  Maegen A. Forrer

IPC: H04L9/32 ,  H04L9/08 ,  G09C1/10

Abstract: A multi-die device a first die containing a plurality of first die signal path elements configured to propagate a stimulus signal and a second die containing a plurality of second die signal path elements configured to propagate the stimulus signal. The multi-die device further includes an interposer configured to establish signal communication between the first die and the second die so as to deliver the stimulus signal from the plurality of first die signal path elements to the plurality of second die signal path elements to generate a propagation delay. The propagation delay is used to generate a single unified PUF response that is indicative of the authenticity of the multi-die device.