公开(公告)号：US20210089453A1

公开(公告)日：2021-03-25

申请号：US17112702

申请日：2020-12-04

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuki HAYAKAWA ,  Toshiyuki KAYA ,  Shinichi SHIBAHARA

IPC: G06F12/0815 ,  G06F12/06 ,  G06F11/16

Abstract: A semiconductor device includes first and second CPUs, first and second SPUs for controlling a snoop operation, a controller supporting ASIL D of a functional safety standard and a memory. The controller sets permission of the snoop operation to the first and second SPUs when a software lock-step is not performed. The controller sets prohibition of the snoop operation to the first and second SPUs when the software lock-step is performed. The first CPU executes a first software for the software lock-step, and writes an execution result in a first area for the memory. The second CPU executes a second software for the software lock-step, and writes an execution result in a second area of the memory. The execution result written in the first area is compared with the execution result written in the second area.

公开(公告)号：US20200073806A1

公开(公告)日：2020-03-05

申请号：US16446195

申请日：2019-06-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuki HAYAKAWA ,  Toshiyuki KAYA ,  Shinichi SHIBAHARA

IPC: G06F12/0815 ,  G06F12/06

Abstract: A semiconductor device includes first and second CPUs, first and second SPUs for controlling a snoop operation, a controller supporting ASIL D of a functional safety standard and a memory. The controller sets permission of the snoop operation to the first and second SPUs when a software lock-step is not performed. The controller sets prohibition of the snoop operation to the first and second SPUs when the software lock-step is performed. The first CPU executes a first software for the software lock-step, and writes an execution result in a first area for the memory. The second CPU executes a second software for the software lock-step, and writes an execution result in a second area of the memory. The execution result written in the first area is compared with the execution result written in the second area.

公开(公告)号：US20240143465A1

公开(公告)日：2024-05-02

申请号：US18452305

申请日：2023-08-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kiyoshi HAYASE ,  Yuki HAYAKAWA ,  Toshiyuki KAYA ,  Kyohei YAMAGUCHI ,  Takahiro IRITA ,  Shinichi SHIBAHARA

IPC: G06F11/22

CPC classification number: G06F11/2284

Abstract: A semiconductor device includes first and second processor cores configured to perform a lock step operation and including first and second scan chains. The semiconductor device further includes a scan test control unit that controls a scan test of the first and second processor cores using the first and second scan chains, and a start-up control unit that outputs a reset signal for bringing the first and second processor cores into a reset state. The start-up control unit outputs an initialization scan request before the start of a lock step operation, and the scan test control unit performs an initialization scan test operation on the first and second processor cores by using an initialization pattern.

公开(公告)号：US20220027225A1

公开(公告)日：2022-01-27

申请号：US17494630

申请日：2021-10-05

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kiyoshi HAYASE ,  Shinichi SHIBAHARA ,  Yuki HAYAKAWA ,  Yoichi YUYAMA

IPC: G06F11/07

Abstract: A semiconductor device has a timer unit and a processing unit. The timer unit includes a binary counter, a first converter that converts a first count value output from the binary counter to a gray code to output as first gray code data. The processing unit includes a first synchronizer that captures the first gray code data transferred from the timer unit in synchronization with the system clock signal and outputs the captured first gray code data as second gray code data, and a fault detection unit that generates a data for fault detection based on the first gray code data transferred from the timer unit and compares a second count value based on the second gray code data with a third counter value based on the data for fault detection.

公开(公告)号：US20210334152A1

公开(公告)日：2021-10-28

申请号：US16859463

申请日：2020-04-27

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kiyoshi HAYASE ,  Shinichi SHIBAHARA ,  Yuki HAYAKAWA ,  Yoichi YUYAMA

IPC: G06F11/07

Abstract: A semiconductor device has a timer unit and a processing unit. The timer unit includes a binary counter, a first converter that converts a first count value output from the binary counter to a gray code to output as first gray code data. The processing unit includes a first synchronizer that captures the first gray code data transferred from the timer unit in synchronization with the system clock signal and outputs the captured first gray code data as second gray code data, and a fault detection unit that generates a data for fault detection based on the first gray code data transferred from the timer unit and compares a second count value based on the second gray code data with a third counter value based on the data for fault detection.

公开(公告)号：US20190391943A1

公开(公告)日：2019-12-26

申请号：US16438050

申请日：2019-06-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuki HAYAKAWA ,  Toshiyuki HIRAKI ,  Sho YAMANAKA

IPC: G06F13/374 ,  G06F12/14

Abstract: A master issues an access request to the memory. The memory controller receives the access request via a bus. An access control unit controls an output of the access request issued by the master to the memory controller by the granting an access right. The access control unit manages a number of grantable rights indicating a number to which the access rights can be granted based on a weight of 0 or more and less than 1 according to a probability that the granted access right is used, and grants the access right within a range of the number of grantable rights.

公开(公告)号：US20190391942A1

公开(公告)日：2019-12-26

申请号：US16438078

申请日：2019-06-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuki HAYAKAWA ,  Toshiyuki HIRAKI ,  Sho YAMANAKA

IPC: G06F13/362 ,  G06F13/20 ,  H04L12/403 ,  G06F12/14

Abstract: Even under various conditions, stay of request on a bus is eliminated, and memory efficiency can be improved. Each of a master A, a master B, and a master X issues an access request to a memory. A memory controller receives an access request through a bus. A central bus control unit controls output of an access request issued by a master to the memory controller through granting the master an access right to the memory. The central bus control unit manages the number of rights that can be granted, which indicates the number of the access rights that can be granted, based on an access size of an access request issued by the master to which the access right is granted, and performs grant of the access right within a range of the number of rights that can be granted.