公开(公告)号：US20210365396A1

公开(公告)日：2021-11-25

申请号：US17395945

申请日：2021-08-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Sho YAMANAKA ,  Toshiyuki HIRAKI

IPC: G06F13/362 ,  G06F11/07 ,  G06F13/16 ,  G06F13/38 ,  G06F11/10

Abstract: The master interface generates copy data by copying the first data, and generates an error detection code based on the copy data. The protocol conversion unit generates the second data by converting the first data from the first protocol to the second protocol. The slave interface detects errors in the copy data based on the error detection code. The slave interface also generates the first verification data by performing a conversion from one of the first protocol or the second protocol to the other for one of the second data or copy data. In addition, the slave interface compares the second verification data with the first verification data, using the other of the second data or copy as the second verification data.

公开(公告)号：US20210026788A1

公开(公告)日：2021-01-28

申请号：US17066998

申请日：2020-10-09

Applicant: Renesas Electronics Corporation

Inventor： Sho YAMANAKA ,  Toshiyuki HIRAKI ,  Yoshihiko HOTTA ,  Takahiro IRITA

IPC: G06F13/16 ,  G06F13/362 ,  G06F13/40 ,  G11C11/406

Abstract: A semiconductor device includes a first master and a second master configured to issue requests for accessing to a memory, a first request issuing controller coupled to the first master, and configured to hold the request issued from the first master, a second request issuing controller coupled to the second master, and configured to hold the request issued from the second master, a bus arbiter coupled to the first request issuing controller and the second request issuing controller, a memory controller coupled to the bus arbiter, and including a buffer configured to store the requests issued from the first master and the second master, and a central bus controller configured to grant access rights to the first request issuing controller and the second request issuing controller based on space information of the buffer.

公开(公告)号：US20230161722A1

公开(公告)日：2023-05-25

申请号：US18153061

申请日：2023-01-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Sho YAMANAKA ,  Toshiyuki HIRAKI

IPC: G06F13/362 ,  G06F11/07 ,  G06F11/10 ,  G06F13/16 ,  G06F13/38

CPC classification number: G06F13/362 ,  G06F11/0772 ,  G06F11/1004 ,  G06F13/387 ,  G06F13/1668

Abstract: The master interface generates copy data by copying the first data, and generates an error detection code based on the copy data. The protocol conversion unit generates the second data by converting the first data from the first protocol to the second protocol. The slave interface detects errors in the copy data based on the error detection code. The slave interface also generates the first verification data by performing a conversion from one of the first protocol or the second protocol to the other for one of the second data or copy data. In addition, the slave interface compares the second verification data with the first verification data, using the other of the second data or copy as the second verification data.

公开(公告)号：US20170270063A1

公开(公告)日：2017-09-21

申请号：US15127765

申请日：2015-10-01

Applicant: Renesas Electronics Corporation

Inventor： Sho YAMANAKA ,  Toshiyuki HIRAKI ,  Yoshihiko HOTTA ,  Takahiro IRITA

IPC: G06F13/16 ,  G11C11/406 ,  G06F13/40

CPC classification number: G06F13/1673 ,  G06F13/1605 ,  G06F13/362 ,  G06F13/4068 ,  G11C11/406

Abstract: A semiconductor device according to the present invention includes a plurality of masters (100), a memory controller (400a), a bus that connects the plurality of masters (100) and the memory controller (400a), a QoS information register (610) that stores QoS information of the plurality of masters (100), a right grant number controller (602) that calculates the number of grantable access rights based on space information of a buffer (401) of the memory controller (400a), a right grant selection controller (603a) that selects the master (100) which will be granted the access right based on the QoS information of the QoS information register (610) and the number of grantable rights from the right grant number controller (602), and a request issuing controller (201a) that does not pass a request of the master (100) which has not been granted the access right from the right grant selection controller (603a).

公开(公告)号：US20230146281A1

公开(公告)日：2023-05-11

申请号：US17951294

申请日：2022-09-23

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuo AITA ,  Daisuke KAWAKAMI ,  Toshiyuki HIRAKI

IPC: G11C29/54 ,  G06F12/109

CPC classification number: G11C29/54 ,  G06F12/109 ,  G06F2212/657

Abstract: A semiconductor device includes a processing unit that issue a memory access request with a virtual address, a first and a second memory management unit and a test result storage unit. The first and the second memory management unit are hierarchically provided, and each include address translation unit translating the virtual memory of the memory access request into a physical address and self-test unit testing for the address translation unit. The test result storage unit stores a first self-test result that indicates a result of the first self-test unit and a second self-test result that indicates a result of the second self-test unit.

公开(公告)号：US20210141749A1

公开(公告)日：2021-05-13

申请号：US17150565

申请日：2021-01-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Katsuya MIZUMOTO ,  Toshiyuki HIRAKI ,  Nobuhiko HONDA ,  Sho YAMANAKA ,  Takahiro IRITA ,  Yoshihiko HOTTA

IPC: G06F13/16 ,  G06F13/362 ,  G06F13/18

Abstract: Access control is achieved in consideration of write training. Masters issue access requests including a read request and a write request. A memory controller accesses memory in response to the access requests issued by the maters. A central bus-control system controls the output of the access requests issued by the masters to the memory controller. A training circuit conducts training on the memory while the access to the memory is stopped. The central bus-control system further controls the execution of the training on the memory. During the training, the central bus-control system suppresses the output of the read request to the memory controller from among the access requests issued by the masters.

公开(公告)号：US20190391943A1

公开(公告)日：2019-12-26

申请号：US16438050

申请日：2019-06-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuki HAYAKAWA ,  Toshiyuki HIRAKI ,  Sho YAMANAKA

IPC: G06F13/374 ,  G06F12/14

Abstract: A master issues an access request to the memory. The memory controller receives the access request via a bus. An access control unit controls an output of the access request issued by the master to the memory controller by the granting an access right. The access control unit manages a number of grantable rights indicating a number to which the access rights can be granted based on a weight of 0 or more and less than 1 according to a probability that the granted access right is used, and grants the access right within a range of the number of grantable rights.

公开(公告)号：US20190391942A1

公开(公告)日：2019-12-26

申请号：US16438078

申请日：2019-06-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuki HAYAKAWA ,  Toshiyuki HIRAKI ,  Sho YAMANAKA

IPC: G06F13/362 ,  G06F13/20 ,  H04L12/403 ,  G06F12/14

Abstract: Even under various conditions, stay of request on a bus is eliminated, and memory efficiency can be improved. Each of a master A, a master B, and a master X issues an access request to a memory. A memory controller receives an access request through a bus. A central bus control unit controls output of an access request issued by a master to the memory controller through granting the master an access right to the memory. The central bus control unit manages the number of rights that can be granted, which indicates the number of the access rights that can be granted, based on an access size of an access request issued by the master to which the access right is granted, and performs grant of the access right within a range of the number of rights that can be granted.

公开(公告)号：US20190196997A1

公开(公告)日：2019-06-27

申请号：US16189355

申请日：2018-11-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Sho YAMANAKA ,  Toshiyuki HIRAKI ,  Nobuhiko HONDA

IPC: G06F13/362 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F13/362 ,  G06F12/0835 ,  G06F12/084 ,  G06F13/1605 ,  G06F13/1663 ,  G06F13/1673 ,  G06F13/4068

Abstract: Each master issues an access request including a read request and a write request to a memory. A cache caches the write request issued by the master. A central bus control system performs access control for the read request issued by each master and the write request output by the cache. A central bus control system performs access control for the write request issued by each master. The central bus control system performs access control in accordance with a free situation of a buffer of a memory controller. The central bus control system performs access control in accordance with a free situation of the cache.