公开(公告)号：US20200313000A1

公开(公告)日：2020-10-01

申请号：US16753949

申请日：2017-11-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuya UEJIMA ,  Shiro KAMOHARA ,  Michio ONDA ,  Takashi HASE ,  Tatsuo NISHINO

IPC: H01L29/78 ,  H01L27/12 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/45 ,  H01L29/51 ,  H03F3/45

Abstract: In a semiconductor device according to an embodiment, a thickness of a semiconductor layer of an SOI substrate on which a field effect transistor constituting an analog circuit is formed is set to 2 nm or more and 24 nm or less.

公开(公告)号：US20230147156A1

公开(公告)日：2023-05-11

申请号：US17983576

申请日：2022-11-09

Applicant: Renesas Electronics Corporation

Inventor： Pratama FAJARMEGA ,  Tatsuo NISHINO ,  Takehiro SHIMIZU

IPC: H03M1/46

CPC classification number: H03M1/462

Abstract: A semiconductor device includes an analog-to-digital converter configured to perform a process of sampling an analog input signal and a successive-approximation process, execute an AD conversion process, and output a digital output signal. The AD converter includes an upper DAC, a redundant DAC, a lower DAC, a comparator configured to compare a comparative reference voltage and output voltages of the upper DAC, the redundant DAC and the lower DAC, a control circuit configured to control successive approximations by the upper DAC, the redundant DAC and the lower DAC based on the comparison result of the comparator, and generate a digital output signal, and a correction circuit. The correction circuit includes an error correction circuit configured to correct an error of the upper bit with the redundant bit, and an averaging circuit configured to calculate an average value of conversion values of a plurality of the lower bits supplied multiple times.

公开(公告)号：US20240363750A1

公开(公告)日：2024-10-31

申请号：US18771200

申请日：2024-07-12

Applicant: Renesas Electronics Corporation

Inventor： Kazuya UEJIMA ,  Shiro KAMOHARA ,  Michio ONDA ,  Takashi HASE ,  Tatsuo NISHINO

IPC: H01L29/78 ,  H01L27/12 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/45 ,  H01L29/51 ,  H03F3/45

CPC classification number: H01L29/7838 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/1083 ,  H01L29/42376 ,  H01L29/45 ,  H01L29/517 ,  H03F3/45179

Abstract: In a semiconductor device according to an embodiment, a thickness of a semiconductor layer of an SOI substrate on which a field effect transistor constituting an analog circuit is formed is set to 2 nm or more and 24 nm or less.

公开(公告)号：US20220406936A1

公开(公告)日：2022-12-22

申请号：US17897844

申请日：2022-08-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuya UEJIMA ,  Michio ONDA ,  Takashi HASE ,  Tatsuo NISHINO ,  Shiro KAMOHARA

IPC: H01L29/78 ,  H01L27/12 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/45 ,  H01L29/51 ,  H03F3/45

Abstract: In a semiconductor device according to an embodiment, a thickness of a semiconductor layer of an SOI substrate on which a field effect transistor constituting an analog circuit is formed is set to 2 nm or more and 24 nm or less.