公开(公告)号：US10390305B1

公开(公告)日：2019-08-20

申请号：US15981737

申请日：2018-05-16

Applicant: QUALCOMM Incorporated

Inventor： James Francis Geekie ,  Suyash Ranjan ,  Xu Chi

IPC: H04L12/28 ,  H04W52/02 ,  H04W56/00 ,  H04L29/08

Abstract: Methods, systems, and devices for wireless communication in a user equipment (UE) are described in which a cycle duration of an extended discontinuous reception (eDRX) cycle is determined. The UE enters a sleep state of the eDRX cycle and, based on the determination of the cycle duration, uses a first clock as a timer during the sleep state and uses a second clock as a timing calibrator during the sleep state. The first clock may have a lower power consumption and a higher frequency error, and the second clock may have a higher power consumption and a lower frequency error.

公开(公告)号：US11496138B2

公开(公告)日：2022-11-08

申请号：US17365783

申请日：2021-07-01

Applicant: Qualcomm Incorporated

Inventor： Shunta Iguchi ,  Xu Chi ,  Michael Naone Farias

IPC: H03L7/099 ,  G06F1/04 ,  G06F1/3287 ,  G06F1/3206 ,  G06F1/3296 ,  G06F1/06 ,  G06F1/08 ,  G06F1/324

Abstract: An apparatus is disclosed for providing frequency stabilization. The apparatus includes a first supply voltage node, a second supply voltage node, an oscillator circuit coupled to the first supply voltage node, at least one clock buffer coupled to the second supply voltage node and an output of the oscillator circuit, and at least one load circuit. The at least one clock buffer is configured to selectively be in a disabled state or an enabled state to pass the clock signal to at least one client of multiple clients. The at least one load circuit includes an input coupled to the output of the oscillator circuit. The at least one load circuit also includes an output configured to be coupled to a ground. The at least one load circuit is configured to be connected to the first supply voltage node for at least a portion of time.

公开(公告)号：US20220006464A1

公开(公告)日：2022-01-06

申请号：US17365783

申请日：2021-07-01

Applicant: Qualcomm Incorporated

Inventor： Shunta Iguchi ,  Xu Chi ,  Michael Naone Farias

IPC: H03L7/099 ,  G06F1/04

Abstract: An apparatus is disclosed for providing frequency stabilization. The apparatus includes a first supply voltage node, a second supply voltage node, an oscillator circuit coupled to the first supply voltage node, at least one clock buffer coupled to the second supply voltage node and an output of the oscillator circuit, and at least one load circuit. The at least one clock buffer is configured to selectively be in a disabled state or an enabled state to pass the clock signal to at least one client of multiple clients. The at least one load circuit includes an input coupled to the output of the oscillator circuit. The at least one load circuit also includes an output configured to be coupled to a ground. The at least one load circuit is configured to be connected to the first supply voltage node for at least a portion of time.

公开(公告)号：US09749962B1

公开(公告)日：2017-08-29

申请号：US15190177

申请日：2016-06-23

Applicant: QUALCOMM INCORPORATED

Inventor： Xu Chi ,  Michael Naone Farias ,  Lalitaprasad Daita

IPC: H04W52/02 ,  G06F1/32 ,  H04W88/06

CPC classification number: H04W52/0287 ,  G06F1/06 ,  G06F1/14 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/329 ,  H03B5/04 ,  H03B5/366 ,  H03L1/00 ,  H03L1/02 ,  H04W88/06 ,  Y02D10/171 ,  Y02D70/00

Abstract: Various embodiments of methods and systems for closed loop multimode sleep clock frequency compensation in a portable computing device are disclosed. An exemplary embodiment leverages a modem to determine a frequency shift on a sleep clock signal when a reference clock has transitioned into a power saving mode. Using the frequency shift calculation, a compensation capacitor may be adjusted to deliver a more optimum dummy load on the crystal oscillator when the reference clock is taken offline. The method may iterate through until the actual frequency shift of the sleep clock is within an acceptable tolerance relative to zero and, further, may also set a status bit to indicate that the sleep clock frequency is stable.