公开(公告)号：US20160285454A1

公开(公告)日：2016-09-29

申请号：US14671553

申请日：2015-03-27

Applicant: QUALCOMM Incorporated

Inventor： Vishal Gupta ,  Chifan Yung ,  Joseph Duncan

IPC: H03K19/0185

CPC classification number: H03K19/018507 ,  H03F3/2173 ,  H03F2203/30015 ,  H03F2203/30084 ,  H03F2203/30099 ,  H03F2203/30117 ,  H03F2203/30132 ,  H03K17/102

Abstract: Disclosed is a cascode configuration that moves the gate of the cascode substantially without delay relative to an output node by capacitively coupling the latter onto the cascode gates. The passive coupling eliminates the need for actively driving the gates of the cascode. In some embodiments, the only circuitry needed on the cascode gate may be a biasing circuit that limits the swing on the cascode gate between Vmax and 2×Vmax, where Vmax is a transistor device rating.

Abstract translation: 公开了一种共源共栅结构，其通过将电容耦合到共源共栅电路上而相对于输出节点基本上没有延迟地移动共源共栅的栅极。 无源耦合消除了积极驱动共源共栅的栅极的需要。 在一些实施例中，级联栅极上所需的唯一电路可以是限制Vmax和2×Vmax之间的共源共栅栅极上的摆幅的偏置电路，其中Vmax是晶体管器件额定值。

公开(公告)号：US12118754B2

公开(公告)日：2024-10-15

申请号：US18494099

申请日：2023-10-25

Applicant: QUALCOMM Incorporated

Inventor： Hau Hwang ,  Tushar Sinha Pankaj ,  Vishal Gupta ,  Jisoo Lee

IPC: G06T7/90 ,  G06N3/04 ,  G06N20/00 ,  G06T3/06 ,  G06T3/4015

CPC classification number: G06T7/90 ,  G06N3/04 ,  G06N20/00 ,  G06T3/06 ,  G06T3/4015 ,  G06T2207/20084

Abstract: Techniques are provided for using one or more machine learning systems to process input data including image data. The input data including the image data can be obtained, and at least one machine learning system can be applied to at least a portion of the image data to determine at least one color component value for one or more pixels of at least the portion of the image data. Based on application of the at least one machine learning system to at least the portion of the image data, output image data for a frame of output image data can be generated. The output image data includes at least one color component value for one or more pixels of the frame of output image data. Application of the at least one machine learning system causes the output image data to have a reduced dimensionality relative to the input data.

公开(公告)号：US11836951B2

公开(公告)日：2023-12-05

申请号：US17665281

申请日：2022-02-04

Applicant: QUALCOMM Incorporated

Inventor： Hau Hwang ,  Tushar Sinha Pankaj ,  Vishal Gupta ,  Jisoo Lee

IPC: G06T7/90 ,  G06T3/00 ,  G06N3/04 ,  G06N20/00 ,  G06T3/40

CPC classification number: G06T7/90 ,  G06N3/04 ,  G06N20/00 ,  G06T3/0031 ,  G06T3/4015 ,  G06T2207/20084

Abstract: Techniques are provided for using one or more machine learning systems to process input data including image data. The input data including the image data can be obtained, and at least one machine learning system can be applied to at least a portion of the image data to determine at least one color component value for one or more pixels of at least the portion of the image data. Based on application of the at least one machine learning system to at least the portion of the image data, output image data for a frame of output image data can be generated. The output image data includes at least one color component value for one or more pixels of the frame of output image data. Application of the at least one machine learning system causes the output image data to have a reduced dimensionality relative to the input data.

公开(公告)号：US09647545B2

公开(公告)日：2017-05-09

申请号：US14518617

申请日：2014-10-20

Applicant: QUALCOMM Incorporated

Inventor： Joseph Duncan ,  Srenik Mehta ,  Vishal Gupta ,  Todd Sutton

IPC: H02M3/158 ,  G05F1/59 ,  H04W52/02 ,  H02M1/00 ,  H02M3/157

CPC classification number: H02M3/158 ,  G05F1/59 ,  H02M3/157 ,  H02M2001/0032 ,  H04W52/0274 ,  Y02B70/16 ,  Y02D70/00 ,  Y02D70/142

Abstract: A low standby power DC-DC converter can be powered down during standby mode. The DC-DC converter can be periodically awakened between sleep cycles to check if the output voltage needs to be recharged (refreshed). The duration of the sleep cycles can be varied to accommodate for changing load conditions that would affect the output voltage.

公开(公告)号：US09641077B2

公开(公告)日：2017-05-02

申请号：US14609203

申请日：2015-01-29

Applicant: QUALCOMM Incorporated

Inventor： Chi-Fan Yung ,  Vishal Gupta ,  Joseph Duncan

IPC: H02M3/158 ,  H02M1/32 ,  H02M1/36 ,  H02M3/155 ,  G01R31/40

CPC classification number: H02M3/158 ,  G01R31/40 ,  H02M1/32 ,  H02M1/36 ,  H02M3/155

Abstract: Reliability of a buck power stage may be enhanced by extending the maximum input voltage able to be withstood in the disabled (non-switching) state. During device qualification/testing, a power management unit (PMU) in the disabled state may have its input node subjected to greater than a maximum input voltage permitted for reliability (Vmax). Under such conditions, a force voltage (Vforce) may be selectively applied to the PMU switching node in the disabled state. For a given input voltage (VIN), this reduces voltage across the non-switching transistors of the power stage (and hence the resulting stress) to below Vmax. In certain embodiments, the Vforce applied to the switching node is of a fixed magnitude. In other embodiments, the Vforce applied to the switching node is of a magnitude varying with input voltage. Embodiments may be particularly suited to implement power management for a System-On-Chip (SoC).

公开(公告)号：US09548739B2

公开(公告)日：2017-01-17

申请号：US14671553

申请日：2015-03-27

Applicant: QUALCOMM Incorporated

Inventor： Vishal Gupta ,  Chifan Yung ,  Joseph Duncan

IPC: H03K5/12 ,  H03K3/00 ,  H03K19/0185 ,  H03F3/217 ,  H03K17/10

CPC classification number: H03K19/018507 ,  H03F3/2173 ,  H03F2203/30015 ,  H03F2203/30084 ,  H03F2203/30099 ,  H03F2203/30117 ,  H03F2203/30132 ,  H03K17/102

Abstract: Disclosed is a cascode configuration that moves the gate of the cascode substantially without delay relative to an output node by capacitively coupling the latter onto the cascode gates. The passive coupling eliminates the need for actively driving the gates of the cascode. In some embodiments, the only circuitry needed on the cascode gate may be a biasing circuit that limits the swing on the cascode gate between Vmax and 2×Vmax, where Vmax is a transistor device rating.

Abstract translation: 公开了一种共源共栅结构，其通过将电容耦合到共源共栅电路上而相对于输出节点基本上没有延迟地移动共源共栅的栅极。 无源耦合消除了积极驱动共源共栅的栅极的需要。 在一些实施例中，级联栅极上所需的唯一电路可以是限制Vmax和2×Vmax之间的共源共栅栅极上的摆幅的偏置电路，其中Vmax是晶体管器件额定值。

公开(公告)号：US11263782B2

公开(公告)日：2022-03-01

申请号：US16814783

申请日：2020-03-10

Applicant: QUALCOMM Incorporated

Inventor： Hau Hwang ,  Tushar Sinha Pankaj ,  Vishal Gupta ,  Jisoo Lee

IPC: G06T7/90 ,  G06T3/00 ,  G06N3/04 ,  G06N20/00 ,  G06T3/40

Abstract: Techniques are provided for using one or more machine learning systems to process input data including image data. The input data including the image data can be obtained, and at least one machine learning system can be applied to at least a portion of the image data to determine at least one color component value for one or more pixels of at least the portion of the image data. Based on application of the at least one machine learning system to at least the portion of the image data, output image data for a frame of output image data can be generated. The output image data includes at least one color component value for one or more pixels of the frame of output image data. Application of the at least one machine learning system causes the output image data to have a reduced dimensionality relative to the input data.

公开(公告)号：US20160226379A1

公开(公告)日：2016-08-04

申请号：US14609203

申请日：2015-01-29

Applicant: QUALCOMM Incorporated

Inventor： Chi-Fan Yung ,  Vishal Gupta ,  Joseph Duncan

IPC: H02M3/158

CPC classification number: H02M3/158 ,  G01R31/40 ,  H02M1/32 ,  H02M1/36 ,  H02M3/155

Abstract: Reliability of a buck power stage may be enhanced by extending the maximum input voltage able to be withstood in the disabled (non-switching) state. During device qualification/testing, a power management unit (PMU) in the disabled state may have its input node subjected to greater than a maximum input voltage permitted for reliability (Vmax). Under such conditions, a force voltage (Vforce) may be selectively applied to the PMU switching node in the disabled state. For a given input voltage (VIN), this reduces voltage across the non-switching transistors of the power stage (and hence the resulting stress) to below Vmax. In certain embodiments, the Vforce applied to the switching node is of a fixed magnitude. In other embodiments, the Vforce applied to the switching node is of a magnitude varying with input voltage. Embodiments may be particularly suited to implement power management for a System-On-Chip (SoC).

Abstract translation: 降低功率级的可靠性可以通过延长能够在禁用（非切换）状态下承受的最大输入电压来增强。 在设备鉴定/测试期间，处于禁用状态的电源管理单元（PMU）可能使其输入节点受到大于允许可靠性（Vmax）的最大输入电压。 在这种条件下，可以在禁用状态下，将有效电压（Vforce）选择性地施加到PMU交换节点。 对于给定的输入电压（VIN），这会将功率级的非开关晶体管（因此产生的应力）的电压降低到Vmax以下。 在某些实施例中，施加到交换节点的Vforce具有固定的大小。 在其他实施例中，施加到开关节点的Vforce的大小随输入电压而变化。 实施例可以特别适于实现片上系统（SoC）的功率管理。