公开(公告)号：US09641077B2

公开(公告)日：2017-05-02

申请号：US14609203

申请日：2015-01-29

Applicant: QUALCOMM Incorporated

Inventor： Chi-Fan Yung ,  Vishal Gupta ,  Joseph Duncan

IPC: H02M3/158 ,  H02M1/32 ,  H02M1/36 ,  H02M3/155 ,  G01R31/40

CPC classification number: H02M3/158 ,  G01R31/40 ,  H02M1/32 ,  H02M1/36 ,  H02M3/155

Abstract: Reliability of a buck power stage may be enhanced by extending the maximum input voltage able to be withstood in the disabled (non-switching) state. During device qualification/testing, a power management unit (PMU) in the disabled state may have its input node subjected to greater than a maximum input voltage permitted for reliability (Vmax). Under such conditions, a force voltage (Vforce) may be selectively applied to the PMU switching node in the disabled state. For a given input voltage (VIN), this reduces voltage across the non-switching transistors of the power stage (and hence the resulting stress) to below Vmax. In certain embodiments, the Vforce applied to the switching node is of a fixed magnitude. In other embodiments, the Vforce applied to the switching node is of a magnitude varying with input voltage. Embodiments may be particularly suited to implement power management for a System-On-Chip (SoC).

公开(公告)号：US20160226379A1

公开(公告)日：2016-08-04

申请号：US14609203

申请日：2015-01-29

Applicant: QUALCOMM Incorporated

Inventor： Chi-Fan Yung ,  Vishal Gupta ,  Joseph Duncan

IPC: H02M3/158

CPC classification number: H02M3/158 ,  G01R31/40 ,  H02M1/32 ,  H02M1/36 ,  H02M3/155

Abstract: Reliability of a buck power stage may be enhanced by extending the maximum input voltage able to be withstood in the disabled (non-switching) state. During device qualification/testing, a power management unit (PMU) in the disabled state may have its input node subjected to greater than a maximum input voltage permitted for reliability (Vmax). Under such conditions, a force voltage (Vforce) may be selectively applied to the PMU switching node in the disabled state. For a given input voltage (VIN), this reduces voltage across the non-switching transistors of the power stage (and hence the resulting stress) to below Vmax. In certain embodiments, the Vforce applied to the switching node is of a fixed magnitude. In other embodiments, the Vforce applied to the switching node is of a magnitude varying with input voltage. Embodiments may be particularly suited to implement power management for a System-On-Chip (SoC).

Abstract translation: 降低功率级的可靠性可以通过延长能够在禁用（非切换）状态下承受的最大输入电压来增强。 在设备鉴定/测试期间，处于禁用状态的电源管理单元（PMU）可能使其输入节点受到大于允许可靠性（Vmax）的最大输入电压。 在这种条件下，可以在禁用状态下，将有效电压（Vforce）选择性地施加到PMU交换节点。 对于给定的输入电压（VIN），这会将功率级的非开关晶体管（因此产生的应力）的电压降低到Vmax以下。 在某些实施例中，施加到交换节点的Vforce具有固定的大小。 在其他实施例中，施加到开关节点的Vforce的大小随输入电压而变化。 实施例可以特别适于实现片上系统（SoC）的功率管理。