公开(公告)号：US20170285705A1

公开(公告)日：2017-10-05

申请号：US15086054

申请日：2016-03-31

Applicant: QUALCOMM Incorporated

Inventor： Jason Edward PODAIMA ,  Christophe Denis Bernard AVOINNE ,  Manokanthan SOMASUNDARAM ,  Sina DENA ,  Paul Christopher John WIERCIENSKI ,  Bohuslav RYCHLIK ,  Steven John HALTER ,  Jaya Prakash SUBRAMANIAM GANASAN ,  Myil RAMKUMAR ,  Dipt Ranjan PAL

IPC: G06F1/26 ,  G06F1/10 ,  G06F12/08

CPC classification number: G06F1/266 ,  G06F1/10 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3287 ,  G06F12/08 ,  G06F2212/1028 ,  G06F2212/657 ,  G06F2212/683 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/171

Abstract: Methods and systems are disclosed for full-hardware management of power and clock domains related to a distributed virtual memory (DVM) network. An aspect includes transmitting, from a DVM initiator to a DVM network, a DVM operation, broadcasting, by the DVM network to a plurality of DVM targets, the DVM operation, and, based on the DVM operation being broadcasted to the plurality of DVM targets by the DVM network, performing one or more hardware optimizations comprising: turning on a clock domain coupled to the DVM network or a DVM target of the plurality of DVM targets that is a target of the DVM operation, increasing a frequency of the clock domain, turning on a power domain coupled to the DVM target based on the power domain being turned off, or terminating the DVM operation to the DVM target based on the DVM target being turned off.

公开(公告)号：US20250155916A1

公开(公告)日：2025-05-15

申请号：US18509245

申请日：2023-11-14

Applicant: QUALCOMM Incorporated

Inventor： Vanamali BHAT ,  Amod PHADKE ,  Sina DENA ,  Michael TIPTON ,  Amit ANEJA ,  Prachin Sheshrao BHOYAR

IPC: G06F1/08 ,  B60W50/06

Abstract: A method for a clock monitoring subsystem of a system-on-chip (SoC) supporting dynamic clock scaling and voltage gating is described. The method includes generating a set of clocks. The method also includes routing a selected one of the set of clocks for frequency measurement through one or more clock routing subsystems. The method further includes adjusting a frequency of the selected clock after the selected clock is routed through the clock routing subsystems. The method also includes communicating a sideband signal to indicate the adjusted frequency of the selected clock.

公开(公告)号：US20190324512A1

公开(公告)日：2019-10-24

申请号：US16458940

申请日：2019-07-01

Applicant: QUALCOMM Incorporated

Inventor： Jason Edward PODAIMA ,  Christophe Denis Bernard AVOINNE ,  Manokanthan SOMASUNDARAM ,  Sina DENA ,  Paul Christopher John WIERCIENSKI ,  Bohuslav RYCHLIK ,  Steven John HALTER ,  Jaya Prakash SUBRAMANIAM GANASAN ,  Myil RAMKUMAR ,  Dipti Ranjan PAL

IPC: G06F1/26 ,  G06F1/3287 ,  G06F1/324 ,  G06F1/3234 ,  G06F1/10

Abstract: Methods and systems are disclosed for full-hardware management of power and clock domains related to a distributed virtual memory (DVM) network. An aspect includes transmitting, from a DVM initiator to a DVM network, a DVM operation, broadcasting, by the DVM network to a plurality of DVM targets, the DVM operation, and, based on the DVM operation being broadcasted to the plurality of DVM targets by the DVM network, performing one or more hardware optimizations comprising: turning on a clock domain coupled to the DVM network or a DVM target of the plurality of DVM targets that is a target of the DVM operation, increasing a frequency of the clock domain, turning on a power domain coupled to the DVM target based on the power domain being turned off, or terminating the DVM operation to the DVM target based on the DVM target being turned off.