公开(公告)号：US20240373560A1

公开(公告)日：2024-11-07

申请号：US18310277

申请日：2023-05-01

Applicant: QUALCOMM Incorporated

Inventor： Seongryul CHOI ,  Kuiwon KANG ,  Hong Bok WE ,  Jung Won PARK

IPC: H05K1/18 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

Abstract: In an aspect, a substrate is disclosed that includes an electronic component including a lower planar surface having one or more electronic component terminals, a core having an upper planar surface facing the lower planar surface of the electronic component; a patterned metallization layer over the upper planar surface of the core, wherein the patterned metallization layer is connected to the one or more electronic component terminals at the lower planar surface of the electronic component; one or more dielectric layers disposed over the upper planar surface of the core; and a cavity formed within the one or more dielectric layers, wherein the electronic component is located in the cavity and over the upper planar surface of the core.

公开(公告)号：US20240373562A1

公开(公告)日：2024-11-07

申请号：US18310408

申请日：2023-05-01

Applicant: QUALCOMM Incorporated

Inventor： Seongryul CHOI ,  Kuiwon KANG ,  Jung Won PARK

IPC: H05K1/18 ,  H05K1/11 ,  H05K3/32 ,  H05K3/40

Abstract: In an aspect, an electronic device is disclosed that includes a core having an upper planar surface and an interior planar surface; a cavity extending at least partially through the upper planar surface of the core to the interior planar surface of the core; an electronic component mounted in the cavity, the electronic component including an upper planar surface having one or more electronic component terminals, wherein the electronic component is supported by the interior planar surface of the core so that the upper planar surface of the electronic component is level with the upper planar surface of the core; and an upper metallization structure configured to provide one or more conductive paths from the one or more electronic component terminals to one or more upper metal terminals of the upper metallization structure.

公开(公告)号：US20240373561A1

公开(公告)日：2024-11-07

申请号：US18310324

申请日：2023-05-01

Applicant: QUALCOMM Incorporated

Inventor： Jung Won PARK ,  Kuiwon KANG ,  Seongryul CHOI

IPC: H05K1/18 ,  H05K3/28

Abstract: In an aspect, an electronic device is disclosed that includes a substrate comprising a core having an upper planar surface and a lower planar surface, wherein the core includes a cavity extending between the upper planar surface of the core and the lower planar surface of the core; an electronic component at least partially disposed in the cavity, wherein the electronic component is at least partially surrounded in the cavity by a cured plugging ink, the electronic component including an upper planar surface having one or more electronic component terminals; and an upper metallization structure configured to provide one or more conductive paths from the one or more electronic component terminals to one or more upper metal terminals of the upper metallization structure.

公开(公告)号：US20210057397A1

公开(公告)日：2021-02-25

申请号：US16546158

申请日：2019-08-20

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon KANG ,  Seongryul CHOI ,  Haekyun KIM

IPC: H01L25/16 ,  H01L23/498 ,  H01L23/13 ,  H01L23/00 ,  H01L21/48

Abstract: An electronic assembly is disclosed that includes an electrodeless passive component embedded in a cavity of a multilayer substrate, wherein the cavity has conductive elements formed on at least two sidewalls of the cavity. The conductive elements are configured to be electrically coupled to the electrodeless passive component. The electrodeless passive component may be located in a first metal layer adjacent an external surface of the multilayer substrate.

公开(公告)号：US20180323137A1

公开(公告)日：2018-11-08

申请号：US15678698

申请日：2017-08-16

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon KANG ,  Houssam JOMAA ,  Layal ROUHANA ,  Seongryul CHOI

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L21/561 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/5384

Abstract: A device comprising a semiconductor die, a package substrate coupled to the semiconductor die, and an encapsulation layer that at least partially encapsulates the semiconductor die. The package substrate includes at least one stacked via. The at least one stacked via includes a first via and a second via coupled to the first via. The second via includes a seed layer coupled to the first via. The second via includes a different shape than the first via. The package substrate includes a prepreg layer. The package substrate includes a first pad coupled to the first via, and a second pad coupled to the second via.