公开(公告)号：US20200013706A1

公开(公告)日：2020-01-09

申请号：US16189128

申请日：2018-11-13

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon KANG ,  Houssam JOMAA

IPC: H01L23/498 ,  H01L21/48

Abstract: A substrate that includes a first substrate portion, a second substrate portion and a second dielectric layer. The first substrate portion includes a core layer having a first core surface, and a plurality of core substrate interconnects, wherein the plurality of core substrate interconnects includes a plurality of surface core substrate interconnects formed over the first surface of core layer. The second substrate portion includes a first dielectric layer having a first dielectric surface, the first dielectric surface facing the first core surface of the core layer, and a plurality of substrate interconnects, wherein the plurality of substrate interconnects includes a plurality of interconnects formed over the first dielectric surface. The second dielectric layer is formed between the first substrate portion and the second substrate portion such that the plurality of surface core substrate interconnects and the plurality of substrate interconnects are located in the second dielectric layer.

公开(公告)号：US20180323137A1

公开(公告)日：2018-11-08

申请号：US15678698

申请日：2017-08-16

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon KANG ,  Houssam JOMAA ,  Layal ROUHANA ,  Seongryul CHOI

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L21/561 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/5384

Abstract: A device comprising a semiconductor die, a package substrate coupled to the semiconductor die, and an encapsulation layer that at least partially encapsulates the semiconductor die. The package substrate includes at least one stacked via. The at least one stacked via includes a first via and a second via coupled to the first via. The second via includes a seed layer coupled to the first via. The second via includes a different shape than the first via. The package substrate includes a prepreg layer. The package substrate includes a first pad coupled to the first via, and a second pad coupled to the second via.

公开(公告)号：US20200051907A1

公开(公告)日：2020-02-13

申请号：US16230896

申请日：2018-12-21

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon KANG ,  Marcus HSU ,  Brigham NAVAJA ,  Houssam JOMAA

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/528 ,  H01L21/768

Abstract: A device that includes a die and a substrate coupled to the die. The substrate includes a dielectric layer and a plurality of embedded interconnects. Each embedded interconnect located through a first planar surface of the substrate such that a first portion of the embedded interconnect is located within the dielectric layer and a second portion of the embedded interconnect is external of the dielectric layer. In some implementations, the substrate includes a core layer. In some implementations, the dielectric layer and the plurality of embedded interconnects may be part of a build up layer of the substrate.

公开(公告)号：US20180269186A1

公开(公告)日：2018-09-20

申请号：US15867518

申请日：2018-01-10

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon KANG ,  Houssam JOMAA ,  Christopher BAHR ,  Layal ROUHANA

IPC: H01L25/10 ,  H01L23/538 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00

Abstract: A package that includes a substrate comprising an interposer interconnect and a cavity, a redistribution portion coupled to the substrate, the redistribution comprising a plurality of redistribution interconnects, and a first die coupled to the redistribution portion through the cavity of the substrate. A substantial region between a side surface of the first die and the substrate is free of an encapsulation layer. In some implementations, the substrate is free of a metal ring that surrounds the first die. In some implementations, the redistribution portion comprises a barrier layer and a first interconnect coupled to the barrier layer. The barrier layer is coupled to the interposer interconnect.