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    LTE CELL SEARCH AND BLUETOOTH eSCO COEXISTENCE USING SHARED ANTENNA
    1.
    发明申请
    LTE CELL SEARCH AND BLUETOOTH eSCO COEXISTENCE USING SHARED ANTENNA 有权
    LTE细胞搜索和蓝牙eSCO共享使用共享天线

    公开(公告)号：US20160119797A1

    公开(公告)日：2016-04-28

    申请号：US14522899

    申请日：2014-10-24

    Applicant: QUALCOMM Incorporated

    Inventor： Soumya Das ,  Nitinkumar Barot

    IPC: H04W24/02 ,  H04W48/16 ,  H04W4/00 ,  H04W24/08

    CPC classification number: H04W24/02 ,  H04W4/80 ,  H04W24/08 ,  H04W48/16 ,  H04W88/06

    Abstract: A UE may use a same antenna for both Bluetooth communications and WWAN cell search and measurement operations. In order to avoid interference, the UE may adjust the periodicity of the WWAN cell search and measurement operations. Adjustment of the WWAN cell search and measurement periodicity may be based on a link quality of the Bluetooth communications.

    Abstract translation: UE可以对蓝牙通信和WWAN小区搜索和测量操作使用相同的天线。 为了避免干扰，UE可以调整WWAN小区搜索和测量操作的周期。 WWAN小区搜索和测量周期的调整可以基于蓝牙通信的链路质量。

    CONCURRENT ACCESS TO MEMORY SPACE BY MULTIPLE INTERFACES
    2.
    发明申请
    CONCURRENT ACCESS TO MEMORY SPACE BY MULTIPLE INTERFACES 有权
    通过多个接口同时访问存储空间

    公开(公告)号：US20170024143A1

    公开(公告)日：2017-01-26

    申请号：US14805185

    申请日：2015-07-21

    Applicant: QUALCOMM Incorporated

    Inventor： Nitinkumar Barot ,  Yifan Li

    IPC: G06F3/06 ,  G06F12/02 ,  G06F12/06

    CPC classification number: G06F3/0611 ,  G06F3/0644 ,  G06F3/0685 ,  G06F9/50 ,  G06F12/00 ,  G06F12/02 ,  G06F12/023 ,  G06F12/0623 ,  G06F13/16 ,  G06F2212/1016 ,  G06F2212/1028 ,  G06F2212/205 ,  G06F2212/601

    Abstract: System, methods and apparatus are described that facilitate access to a memory device. A memory space within the memory device is divided into a plurality of storage bank domains. Thereafter, application interface circuits configured to access the memory space are classified into a plurality of interface groups based on one or more application usage requirements. Each interface group of the plurality of interface groups is assigned to a corresponding storage bank domain from the plurality of storage bank domains. Access between each interface group and the corresponding storage bank domain is then provided, wherein a first application interface circuit of a first interface group accesses a first corresponding storage bank domain while a second application interface circuit of a second interface group accesses a second corresponding storage bank domain.

    Abstract translation: 描述了便于访问存储器件的系统，方法和装置。 存储器装置内的存储器空间被分成多个存储库域。 此后，基于一个或多个应用使用要求将被配置为访问存储器空间的应用接口电路分类为多个接口组。 多个接口组中的每个接口组从多个存储库域分配给相应的存储库域。 然后提供每个接口组与相应的存储区域之间的接入，其中第一接口组的第一应用接口电路访问第一对应的存储区域，而第二接口组的第二应用接口电路访问第二对应存储体 域。

    TWO-WIRE LINE-MULTIPLEXED UART TO FOUR-WIRE HIGH-SPEED UART BRIDGING WITH INTEGRATED FLOW CONTROL
    4.
    发明申请
    TWO-WIRE LINE-MULTIPLEXED UART TO FOUR-WIRE HIGH-SPEED UART BRIDGING WITH INTEGRATED FLOW CONTROL 审中-公开

    公开(公告)号：US20170329737A1

    公开(公告)日：2017-11-16

    申请号：US15151682

    申请日：2016-05-11

    Applicant: QUALCOMM Incorporated

    Inventor： Nitinkumar Barot ,  Lalan Jee Mishra ,  Richard Dominic Wietfeldt

    IPC: G06F13/42 ,  G06F13/362

    CPC classification number: G06F13/4282 ,  G06F13/362 ,  G06F13/405

    Abstract: Systems, methods, and apparatus for bridging between different types of serial interface are disclosed. A method performed by a bridge circuit includes synchronizing transmissions on a 4-wire serial interface with transmissions on a 2-wire serial interface when a stop bit is detected on data lines of at least one interface, receiving a first clear-to-send notification from a first wire of the 2-wire serial interface, asserting a request-to-send signal on a first flow-control line of the 4-wire serial interface, receiving data bits from a first data line of the 4-wire serial interface while the request-to-send signal is asserted, and transmitting the data bits on the first wire of the 2-wire serial interface after receiving the first clear-to-send notification.

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