公开(公告)号：US10061542B2

公开(公告)日：2018-08-28

申请号：US14855319

申请日：2015-09-15

Applicant: QUALCOMM Incorporated

Inventor： Tony Chung Yiu Kwok ,  Nishith Nitin Desai ,  Changho Jung

IPC: G06F3/06 ,  G11C11/419 ,  G11C7/10 ,  G11C7/22 ,  G06F13/16

CPC classification number: G06F3/0683 ,  G06F3/0611 ,  G06F3/0659 ,  G06F13/1689 ,  G11C7/1075 ,  G11C7/22 ,  G11C11/419

Abstract: Aspects of a memory and method for accessing the memory are disclosed. The memory includes a plurality of memory cells configured to support a read and write operation in a memory cycle in a first mode and a write only operation in the memory cycle in a second mode. The memory further includes a control circuit configured to generate a read clock for the read operation and a write clock for the write operation. The timing of the write clock is a function of the timing of the read clock in the first mode, and the timing of the memory cycle in the second mode.

公开(公告)号：US09520165B1

公开(公告)日：2016-12-13

申请号：US14745216

申请日：2015-06-19

Applicant: QUALCOMM Incorporated

Inventor： Nishith Nitin Desai ,  Tony Chung Yiu Kwok ,  Changho Jung

IPC: G11C7/12 ,  G11C11/4094 ,  G11C11/419

CPC classification number: G11C7/12 ,  G11C7/08 ,  G11C11/419 ,  G11C2207/002

Abstract: A pseudo-dual-port (PDP) memory such as a PDP SRAM is provided that independently controls the bit line precharging and the sense amplifier precharging to increase memory operating speed while eliminating or reducing the discharge of crowbar current.

Abstract translation: 提供诸如PDP SRAM的伪双端口（PDP）存储器，其独立地控制位线预充电和感测放大器预充电以增加存储器操作速度，同时消除或减少撬棒电流的放电。

公开(公告)号：US20160372167A1

公开(公告)日：2016-12-22

申请号：US14745216

申请日：2015-06-19

Applicant: QUALCOMM Incorporated

Inventor： Nishith Nitin Desai ,  Tony Chung Yiu Kwok ,  Changho Jung

IPC: G11C7/12 ,  G11C11/419

CPC classification number: G11C7/12 ,  G11C7/08 ,  G11C11/419 ,  G11C2207/002

Abstract: A pseudo-dual-port (PDP) memory such as a PDP SRAM is provided that independently controls the bit line precharging and the sense amplifier precharging to increase memory operating speed while eliminating or reducing the discharge of crowbar current.

Abstract translation: 提供诸如PDP SRAM的伪双端口（PDP）存储器，其独立地控制位线预充电和感测放大器预充电以增加存储器操作速度，同时消除或减少撬棒电流的放电。

公开(公告)号：US09324416B2

公开(公告)日：2016-04-26

申请号：US14464627

申请日：2014-08-20

Applicant: QUALCOMM Incorporated

Inventor： Sei Seung Yoon ,  Tony Chung Yiu Kwok ,  Changho Jung ,  Nishith Nitin Desai

IPC: G11C16/04 ,  G11C11/419 ,  G11C7/10 ,  G11C7/22

CPC classification number: G11C11/419 ,  G11C7/106 ,  G11C7/1072 ,  G11C7/1075 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222 ,  G11C8/16 ,  G11C11/412

Abstract: A memory and a method for operating the memory provided. In one aspect, the memory may be a PDP memory. The memory includes a control circuit configured to generate a first clock and a second clock in response an edge of a clock for an access cycle. A first input circuit is configured to receive an input for a first memory access based on the first clock. The first input circuit includes a latch. The second input circuit configured to receive an input for a second memory access based on the second clock. The second input circuit includes a flip-flop.

Abstract translation: 用于操作所提供的存储器的存储器和方法。 在一个方面，存储器可以是PDP存储器。 存储器包括控制电路，该控制电路经配置以响应于访问周期的时钟的边沿而产生第一时钟和第二时钟。 第一输入电路被配置为基于第一时钟接收用于第一存储器访问的输入。 第一输入电路包括锁存器。 第二输入电路被配置为基于第二时钟接收用于第二存储器访问的输入。 第二输入电路包括触发器。