公开(公告)号：US20170075379A1

公开(公告)日：2017-03-16

申请号：US14855319

申请日：2015-09-15

Applicant: QUALCOMM Incorporated

Inventor： Tony Chung Yiu KWOK ,  Nishith Nitin DESAI ,  Changho JUNG

IPC: G06F1/12 ,  G06F3/06

CPC classification number: G06F3/0683 ,  G06F3/0611 ,  G06F3/0659 ,  G06F13/1689 ,  G11C7/1075 ,  G11C7/22 ,  G11C11/419

Abstract: Aspects of a memory and method for accessing the memory are disclosed. The memory includes a plurality of memory cells configured to support a read and write operation in a memory cycle in a first mode and a write only operation in the memory cycle in a second mode. The memory further includes a control circuit configured to generate a read clock for the read operation and a write clock for the write operation. The timing of the write clock is a function of the timing of the read clock in the first mode, and the timing of the memory cycle in the second mode.

Abstract translation: 公开了用于访问存储器的存储器和方法的方面。 存储器包括多个存储器单元，其被配置为在第一模式的存储器循环中支持读和写操作，并且在第二模式中在存储器循环中支持只读操作。 存储器还包括控制电路，其被配置为产生用于读取操作的读取时钟和用于写入操作的写入时钟。 写时钟的定时是第一模式中的读时钟的定时和第二模式中的存储器周期的定时的函数。

公开(公告)号：US20160055903A1

公开(公告)日：2016-02-25

申请号：US14464627

申请日：2014-08-20

Applicant: QUALCOMM Incorporated

Inventor： Sei Seung YOON ,  Tony Chung Yiu KWOK ,  Changho JUNG ,  Nishith Nitin DESAI

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C7/106 ,  G11C7/1072 ,  G11C7/1075 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222 ,  G11C8/16 ,  G11C11/412

Abstract: A memory and a method for operating the memory provided. In one aspect, the memory may be a PDP memory. The memory includes a control circuit configured to generate a first clock and a second clock in response an edge of a clock for an access cycle. A first input circuit is configured to receive an input for a first memory access based on the first clock. The first input circuit includes a latch. The second input circuit configured to receive an input for a second memory access based on the second clock. The second input circuit includes a flip-flop.

Abstract translation: 用于操作所提供的存储器的存储器和方法。 在一个方面，存储器可以是PDP存储器。 存储器包括控制电路，该控制电路经配置以响应于访问周期的时钟的边沿而产生第一时钟和第二时钟。 第一输入电路被配置为基于第一时钟接收用于第一存储器访问的输入。 第一输入电路包括锁存器。 第二输入电路被配置为基于第二时钟接收用于第二存储器访问的输入。 第二输入电路包括触发器。

公开(公告)号：US20150294694A1

公开(公告)日：2015-10-15

申请号：US14251495

申请日：2014-04-11

Applicant: QUALCOMM Incorporated

Inventor： Changho JUNG ,  Tony Chung Yiu KWOK ,  Nishith Nitin DESAI

IPC: G11C5/06 ,  G11C7/10

CPC classification number: G11C5/063 ,  G11C8/16 ,  H01L27/0207 ,  H01L27/1104 ,  H01L27/11807 ,  H01L2027/11838

Abstract: A CMOS apparatus includes a first transistor having a first transistor gate, a second transistor having a second transistor gate, a partial transistor having a gate and only one of a drain or a source. The CMOS apparatus further includes a gate interconnect connecting the first transistor gate to the second transistor gate through the gate of the partial transistor. The CMOS apparatus may be a bit cell. A write word enable line may include the gate interconnect, and the first and second transistors may enable write bit lines to the bit cell.

Abstract translation: CMOS器件包括具有第一晶体管栅极的第一晶体管，具有第二晶体管栅极的第二晶体管，具有栅极且仅漏极或源极之一的部分晶体管。 CMOS器件还包括通过部分晶体管的栅极将第一晶体管栅极连接到第二晶体管栅极的栅极互连。 CMOS装置可以是位单元。 写字使能线可以包括栅极互连，并且第一和第二晶体管可以使能到位单元的写位线。