公开(公告)号：US10454665B2

公开(公告)日：2019-10-22

申请号：US15924066

申请日：2018-03-16

Applicant: Qualcomm Incorporated

Inventor： Shunta Iguchi ,  Ilker Deligoz ,  Michael Naone Farias

IPC: H04L7/00 ,  H03B5/36 ,  H04B1/40 ,  H03G3/00 ,  H03K17/687

Abstract: An apparatus is disclosed for hybrid-controlled clock generation. In an example aspect, the apparatus includes an analog control circuit, a digital control circuit, a transistor array, an oscillator circuit, and a selection circuit. The oscillator circuit is coupled to the transistor array. The selection circuit includes a first input that is coupled to the analog control circuit, a second input that is coupled to the digital control circuit, and an output that is coupled to the transistor array. The selection circuit is configured to obtain a selection signal that is indicative of the first input coupled to the analog control circuit or the second input coupled to the digital control circuit. The selection circuit is also configured to connect, based on the selection signal, the analog control circuit or the digital control circuit to the transistor array.

公开(公告)号：US11480992B1

公开(公告)日：2022-10-25

申请号：US17154726

申请日：2021-01-21

Applicant: QUALCOMM Incorporated

Inventor： Jize Jiang ,  Ilker Deligoz

IPC: G06F1/06 ,  G05F1/46 ,  H04B1/40 ,  H03F3/24

Abstract: Certain aspects of the present disclosure provide a circuit for clock signal generation. The circuit generally includes a plurality of clock generation circuits configured to generate a plurality of clock signals from a clock signal, and a power supply circuit having an output coupled to power supply inputs of the plurality of clock generation circuits. The circuit may also include a capacitor array coupled to the output of the power supply circuit and include a plurality of capacitive elements, the capacitor array being configured to selectively couple each of the plurality of capacitive elements to the output of the power supply circuit based on a quantity of one or more active clock generation circuits of the plurality of clock generation circuits.

公开(公告)号：US10727838B2

公开(公告)日：2020-07-28

申请号：US16035024

申请日：2018-07-13

Applicant: QUALCOMM Incorporated

Inventor： Terrence Brian Remple ,  Ilker Deligoz

IPC: H03L7/07 ,  G06F1/10 ,  H03L7/08 ,  H03L7/099

Abstract: Power conservation in a phase locked loop (PLL) places the PLL into a low-power mode and periodically reactivates the PLL to prevent leakage current from causing a voltage controlled oscillator (VCO) within the PLL to drift. The PLL also includes an adjustable delay circuit positioned between an output of the VCO and an input of a phase detector, where the delay circuit is used to adjust phase slew of a feedback signal to help the PLL settle into a desired frequency. By controlling the drift of the VCO and keeping the phase slew of the feedback signal to a minimum, the PLL may be activated and settle to a desired frequency within a relatively short amount of time. By keeping this time so short, the PLL may be placed into and pulled out of a low-power mode and still meet rigid timing requirements of various transmission protocols.

公开(公告)号：US20190288829A1

公开(公告)日：2019-09-19

申请号：US15924066

申请日：2018-03-16

Applicant: Qualcomm Incorporated

Inventor： Shunta Iguchi ,  Ilker Deligoz ,  Michael Naone Farias

IPC: H04L7/00 ,  H03B5/36 ,  H03K17/687 ,  H03G3/00 ,  H04B1/40

Abstract: An apparatus is disclosed for hybrid-controlled clock generation. In an example aspect, the apparatus includes an analog control circuit, a digital control circuit, a transistor array, an oscillator circuit, and a selection circuit. The oscillator circuit is coupled to the transistor array. The selection circuit includes a first input that is coupled to the analog control circuit, a second input that is coupled to the digital control circuit, and an output that is coupled to the transistor array. The selection circuit is configured to obtain a selection signal that is indicative of the first input coupled to the analog control circuit or the second input coupled to the digital control circuit. The selection circuit is also configured to connect, based on the selection signal, the analog control circuit or the digital control circuit to the transistor array.

公开(公告)号：US11181939B2

公开(公告)日：2021-11-23

申请号：US16420723

申请日：2019-05-23

Applicant: Qualcomm Incorporated

Inventor： Shunta Iguchi ,  Ilker Deligoz ,  Michael Naone Farias

IPC: H03L5/02 ,  H03B5/36 ,  G06F1/08 ,  H03B5/02 ,  H03B5/12

Abstract: An apparatus is disclosed for implementing multi-mode oscillation circuitry with stepping control. In an example aspect, the multi-mode oscillation circuitry comprises a resonator coupled to a first oscillator and a second oscillator. The multi-mode oscillation circuitry is configured to selectively be in a first configuration with the first oscillator in an active state and the second oscillator in an inactive state or a second configuration with the first oscillator in the inactive state and the second oscillator in the active state. The apparatus also includes a step-control circuit coupled to the multi-mode oscillation circuitry. The step-control circuit is configured to cause the first oscillator to switch from the inactive state to the active state and incrementally increase a first gain of the first oscillator based on the first oscillator being in the active state to enable the multi-mode oscillation circuitry to transition from the second configuration to the first configuration.

公开(公告)号：US20200371545A1

公开(公告)日：2020-11-26

申请号：US16420723

申请日：2019-05-23

Applicant: Qualcomm Incorporated

Inventor： Shunta Iguchi ,  Ilker Deligoz ,  Michael Naone Farias

IPC: G06F1/08 ,  H03B5/02 ,  H03B5/12

Abstract: An apparatus is disclosed for implementing multi-mode oscillation circuitry with stepping control. In an example aspect, the multi-mode oscillation circuitry comprises a resonator coupled to a first oscillator and a second oscillator. The multi-mode oscillation circuitry is configured to selectively be in a first configuration with the first oscillator in an active state and the second oscillator in an inactive state or a second configuration with the first oscillator in the inactive state and the second oscillator in the active state. The apparatus also includes a step-control circuit coupled to the multi-mode oscillation circuitry. The step-control circuit is configured to cause the first oscillator to switch from the inactive state to the active state and incrementally increase a first gain of the first oscillator based on the first oscillator being in the active state to enable the multi-mode oscillation circuitry to transition from the second configuration to the first configuration.

公开(公告)号：US20200021295A1

公开(公告)日：2020-01-16

申请号：US16035024

申请日：2018-07-13

Applicant: QUALCOMM Incorporated

Inventor： Terrence Brian Remple ,  Ilker Deligoz

IPC: H03L7/07 ,  G06F1/10 ,  H03L7/099 ,  H03L7/08

Abstract: Power conservation in a phase locked loop (PLL) places the PLL into a low-power mode and periodically reactivates the PLL to prevent leakage current from causing a voltage controlled oscillator (VCO) within the PLL to drift. The PLL also includes an adjustable delay circuit positioned between an output of the VCO and an input of a phase detector, where the delay circuit is used to adjust phase slew of a feedback signal to help the PLL settle into a desired frequency. By controlling the drift of the VCO and keeping the phase slew of the feedback signal to a minimum, the PLL may be activated and settle to a desired frequency within a relatively short amount of time. By keeping this time so short, the PLL may be placed into and pulled out of a low-power mode and still meet rigid timing requirements of various transmission protocols.