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    Method, devices and systems for dynamic multimedia data flow control for thermal power budgeting
    1.
    发明授权
    Method, devices and systems for dynamic multimedia data flow control for thermal power budgeting 有权

    公开(公告)号：US09703355B2

    公开(公告)日：2017-07-11

    申请号：US14034725

    申请日：2013-09-24

    申请人： QUALCOMM Incorporated

    发明人： Hee-Jun Park ,  Dam Backer

    IPC分类号： G06F13/36 ,  G06F15/173 ,  G06F1/32

    CPC分类号： G06F1/3212 ,  G06F1/3206 ,  G06F1/3234

    摘要： Methods and devices for managing data flows for concurrent multimedia applications executing on a device including a SoC, in response to determining that a temperature or power consumption exceeds a threshold are disclosed. A lowest priority data flow may be identified. A data flow path associated with the identified lowest priority data flow may be traced. A multimedia parameter of any hardware module along the data flow path may be reduced. When the temperature or power consumption no longer exceeds the threshold, a highest priority data flow among the multimedia applications that has had the multimedia parameter reduced may be identified. A data flow path for a data flow associated with the identified highest priority data flow may be traced. The multimedia parameter may be restored to an original value along the traced data flow path for the data flow associated with the identified highest priority data flow.

    DITHERED VARIABLE RATE SHADING
    4.
    发明申请
    DITHERED VARIABLE RATE SHADING 审中-公开

    公开(公告)号：US20190035049A1

    公开(公告)日：2019-01-31

    申请号：US15954384

    申请日：2018-04-16

    申请人： QUALCOMM Incorporated

    发明人： Dam Backer ,  Brian Ellis ,  Bozhan Chen

    IPC分类号： G06T1/20

    摘要： Aspects of this disclosure relate to a device for generating image content that includes a memory and processing circuitry coupled to the memory. The processing circuitry is configured to determine a dithered fractional VRS value for a core block based on a dithering factor for the core block and a fractional VRS value for the core block and determine a dithered fractional shading rate based on the dithered fractional VRS value. The processing circuitry is further configured to render the image based on the dithered fractional shading rate.

    SCHEDULING IMAGE COMPOSITION IN A PROCESSOR BASED ON OVERLAPPING OF AN IMAGE COMPOSITION PROCESS AND AN IMAGE SCAN-OUT OPERATION FOR DISPLAYING A COMPOSED IMAGE
    5.
    发明申请
    SCHEDULING IMAGE COMPOSITION IN A PROCESSOR BASED ON OVERLAPPING OF AN IMAGE COMPOSITION PROCESS AND AN IMAGE SCAN-OUT OPERATION FOR DISPLAYING A COMPOSED IMAGE 有权

    公开(公告)号：US20210109346A1

    公开(公告)日：2021-04-15

    申请号：US17070410

    申请日：2020-10-14

    申请人： QUALCOMM Incorporated

    发明人： Dam Backer ,  Brian Ellis

    IPC分类号： G02B27/00 ,  G02B27/01

    摘要： Scheduling image composition in a processor based on overlapping of an image composition process and image scan-out operation for displaying an image is disclosed. The processor is configured to periodically schedule a composition process to generate composition passes on the received eyebuffers to generate a display-corrected image for scan-out to a display device. To reduce the motion-to-photon latency, the processor is configured to delay scheduling of the composition process to be closer in time to the scan-out deadline such that there is an overlap in execution of the composition process at the scan-out deadline and image scan-out operation. The scheduling of the composition process can be delayed to only generate a desired number of display lines for the display-corrected image before the scan-out deadline such that lines of the display-corrected image can continue to be available faster than needed for scanning out by the image scan-out operation without scan-out delay.