公开(公告)号：US10353819B2

公开(公告)日：2019-07-16

申请号：US15192416

申请日：2016-06-24

Applicant: QUALCOMM Incorporated

Inventor： Brandon Dwiel ,  Rami Mohammad Al Sheikh

IPC: G06F13/00 ,  G06F12/0862 ,  G06F12/0811 ,  G06F9/38

Abstract: Next line prefetchers employing initial high prefetch prediction confidence states for throttling next line prefetches in processor-based system are disclosed. Next line prefetcher prefetches a next memory line into cache memory in response to read operation. To mitigate prefetch mispredictions, next line prefetcher is throttled to cease prefetching after prefetch prediction confidence state becomes a no next line prefetch state indicating number of incorrect predictions. Instead of initial prefetch prediction confidence state being set to no next line prefetch state, which is built up in response to correct predictions before performing a next line prefetch, initial prefetch prediction confidence state is set to next line prefetch state to allow next line prefetching. Thus, next line prefetcher starts prefetching next lines before requiring correct predictions to be “built up” in prefetch prediction confidence state. CPU performance may be increased, because prefetching begins sooner rather than waiting for correct predictions to occur.

公开(公告)号：US20170371790A1

公开(公告)日：2017-12-28

申请号：US15192416

申请日：2016-06-24

Applicant: QUALCOMM Incorporated

Inventor： Brandon Dwiel ,  Rami Mohammad Al Sheikh

IPC: G06F12/0862 ,  G06F12/0811

CPC classification number: G06F12/0862 ,  G06F9/3802 ,  G06F12/0811 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/283 ,  G06F2212/452 ,  G06F2212/602

Abstract: Next line prefetchers employing initial high prefetch prediction confidence states for throttling next line prefetches in processor-based system are disclosed. Next line prefetcher prefetches a next memory line into cache memory in response to read operation. To mitigate prefetch mispredictions, next line prefetcher is throttled to cease prefetching after prefetch prediction confidence state becomes a no next line prefetch state indicating number of incorrect predictions. Instead of initial prefetch prediction confidence state being set to no next line prefetch state, which is built up in response to correct predictions before performing a next line prefetch, initial prefetch prediction confidence state is set to next line prefetch state to allow next line prefetching. Thus, next line prefetcher starts prefetching next lines before requiring correct predictions to be “built up” in prefetch prediction confidence state. CPU performance may be increased, because prefetching begins sooner rather than waiting for correct predictions to occur.

公开(公告)号：US10379863B2

公开(公告)日：2019-08-13

申请号：US15712119

申请日：2017-09-21

Applicant: QUALCOMM Incorporated

Inventor： Shivam Priyadarshi ,  Rami Mohammad A. Al Sheikh ,  Brandon Dwiel ,  Derek Hower

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/32

Abstract: Systems and methods for constructing an instruction slice for prefetching data of a data-dependent load instruction include a slicer for identifying a load instruction in an instruction sequence as a first occurrence of a qualified load instruction which will miss in a last-level cache. A commit buffer stores information pertaining to the first occurrence of the qualified load instruction and shadow instructions which follow. For a second occurrence of the qualified load instruction, an instruction slice is constructed from the information in the commit buffer to form a slice payload. A pre-execution engine pre-executes the instruction slice based on the slice payload to determine an address from which data is to be fetched for execution of a third and any subsequent occurrences of the qualified load instruction. The data is prefetched from the determined address for the third and any subsequent occurrence of the qualified load instruction.

公开(公告)号：US10303608B2

公开(公告)日：2019-05-28

申请号：US15683391

申请日：2017-08-22

Applicant: QUALCOMM Incorporated

Inventor： Rami Mohammad Al Sheikh ,  Shivam Priyadarshi ,  Brandon Dwiel ,  David John Palframan ,  Derek Hower ,  Muntaquim Faruk Chowdhury

IPC: G06F12/00 ,  G06F13/00 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1045 ,  G06F12/109 ,  G06F9/345 ,  G06F9/38

Abstract: A first load instruction specifying a first virtual address misses in a data cache. A delta value is received based on a program counter value of the first load instruction. A second virtual address is computed based on the delta value and the first virtual address. Data associated with the second virtual address is then prefetched from a main memory to the data cache prior to a second load instruction specifying the second virtual address missing in the data cache.